Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C— May 2003

 

The following sections provide an overview of the power

 

management states . For more details, refer to the

 

AMD Athlon™ and AMD Duron™ System Bus Specification,

 

order# 21902.

 

Note: In all power management states that the processor is

 

powered, the system must not stop the system clock

 

(SYSCLK/SYSCLK#) to the processor.

Working State

The Working state is the state in which the processor is

 

executing instructions.

Halt State

When the processor executes the HLT instruction, the processor

 

enters the Halt state and issues a Halt special cycle to the

 

AMD Athlon system bus. The processor only enters the low

 

power state dictated by the CLK_Ctl MSR if the system

 

controller (Northbridge) disconnects the AMD Athlon system

 

bus in response to the Halt special cycle.

 

If STPCLK# is asserted, the processor will exit the Halt state

 

and enter the Stop Grant state. The processor will initiate a

 

system bus connect, if it is disconnected, then issue a Stop

 

Grant special cycle. When STPCLK# is deasserted, the

 

processor will exit the Stop Grant state and re-enter the Halt

 

state. The processor will issue a Halt special cycle when

 

re-entering the Halt state.

 

The Halt state is exited when the processor detects the

 

assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR

 

or NMI pins, or via a local APIC interrupt message. When the

 

Halt state is exited, the processor will initiate an AMD Athlon

 

system bus connect if it is disconnected.

Stop Grant States The processor enters the Stop Grant state upon recognition of assertion of STPCLK# input. After entering the Stop Grant state, the processor issues a Stop Grant special bus cycle on the AMD Athlon system bus. The processor is not in a low-power state at this time, because the AMD Athlon system bus is still connected. After the Northbridge disconnects the AMD Athlon system bus in response to the Stop Grant special bus cycle, the processor enters a low-power state dictated by the CLK_Ctl MSR. If the Northbridge needs to probe the processor during the Stop Grant state while the system bus is disconnected, it

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Power Management

Chapter 4

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AMD 10, 27493, 27488 manual Working State, Halt State