Exiting the Stop Grant State and Bus Connect Sequence | AMD 27493

Preliminary Information

26237C —May 2003

AMD Athlon™ XP Processor Model 10 Data Sheet

Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state, connects the processor to the AMD Athlon system bus, and puts the processor into the Working state.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus:

1.The Southbridge deasserts STPCLK#, informing the processor of a wake event.

2.When the processor recognizes STPCLK# deassertion, it exits the low-power state and asserts PROCRDY, notifying the Northbridge to connect to the bus.

3.The Northbridge asserts CONNECT.

4.The Northbridge deasserts CLKFWDRST, synchronizing the forwarded clocks between the processor and the Northbridge.

5.The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution.

Chapter 4

Power Management

15

Image 27

AMD 27493, 10, 27488 manual Exiting the Stop Grant State and Bus Connect Sequence

Contents

Data Sheet 2002, 2003 Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information Preliminary Information List of Figures Logic Symbol Diagram Viii List of Tables List of Tables May Revision HistoryDate Rev , revised wording in the Overview Xii Delivering extreme performance for Windows XP Overview QuantiSpeed Architecture Summary LAN Preliminary Information Interface Signals Signaling TechnologyOverview Push-Pull PP Drivers AMD Athlon System Bus Signals Logic Symbol Diagram Frequency Control Front-Side Bus Autodetect LegacyDiode Preliminary Information Power Management States Power Management Halt State Working State Preliminary Information Connect and Disconnect Protocol Probe StateConnect Protocol Preliminary Information Procrdy Exiting the Stop Grant State and Bus Connect Sequence Connect State Diagram Northbridge Connect Pending Disconnect Disconnect4/CDisconnect request Return internal clocks to full speed and assert Clock Control Cpuid Support Preliminary Information 12.1 a MaximumMaximum Typical 68.3 W 53.7 W Duty Cycle Advanced 333 FSB Sysclk and SYSCLK# AC CharacteristicsParameter Description Minimum Maximum Clock Frequency Advanced 333 FSB AMD Athlon System Bus AC Characteristics Advanced 333 FSB AMD Athlon System Bus DC Characteristics Advanced 333 FSB AMD Athlon System Bus DC Characteristics 76.8 W 60.4 W Maximum Typical 2100 3000+12.1 a 68.3 W 53.7 W 2200 3200+ Advanced 400 FSB Sysclk and SYSCLK# AC Characteristics Advanced 400 FSB AMD Athlon System Bus AC Characteristics Advanced 400 FSB AMD Athlon System Bus DC Characteristics Advanced 400 FSB AMD Athlon System Bus DC Characteristics Conventions Interface Signal GroupingsInterface Signal Groupings Electrical Data Voltage Identification VID40 VID40 DC Characteristics Frequency Identification FID30 Vcca AC and DC CharacteristicsFID30 DC Characteristics Vcca AC and DC Characteristics Vcccore AC and DC Characteristics Vcccore Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Input Time to Reacquire Signal Rise TimeSignal Fall Time Input Time to Acquire 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Open Drain Test Circuit Thermal Diode Thermal Diode CharacteristicsCharacteristics Thermal Diode Electrical Characteristics Symbol Parameter Description Max Units Guidelines for Platform Thermal Protection of the Processor500 Apic Pin AC and DC Characteristics Apic Pins AC and DC Characteristics Preliminary Information Power-Up Requirements Signal and Power-Up Requirements Pwrok Preliminary Information Processor Warm Reset Requirements Clock MultiplierSelection FID30 Location Dynamic MAX Static MAX Units Die Surface 100 Mechanical DataDie Loading Mechanical Loading 453 Letter or Minimum Maximum Preliminary Information Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Preliminary Information Preliminary Information Pin Descriptions Pin Diagram and Pin Name Abbreviations AMD Athlon XP Processor Bottomside View Pin Name Abbreviations AD30 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AA31 AC31 AL33 AE33AJ35 AG37 E15 W33J35 E27 F34 F24F28 F32 AM14 AK34AK36 AM10 V36 V30V32 V34 Pin List A35 SDATA40# A37 SDATA30# Cross-Reference by Pin LocationPin Name No Pin NC Pin F10 SDATA52# E11 SDATA50# E13 SDATA49# E15E29 SDATA33# E31 SDATA32# Pin Name E33 NC Pin E35 SDATA31# E37 SDATA22# J37 SDATA29# NC Pin H10 H12H28 NC Pin H30 H32 H34 NC Pin VID4 J31 J33 SDATA19# J35 U31 NC Pin U33 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S31 NC Pin S33 S35 SDATA15# S37 Y37 SDATA12# FID0 FID1NC Pin W31 W33 FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 AF20 NC Pin AD30 AD32AE31 NC Pin AE33 NC Pin AF10 AF12 NC Pin AK10 AH30 FSBSense1 AH32NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 AJ27 NC Pin AJ29 AN11 NC Pin AN13 AL25 NC Pin AL27 AL29NC Pin AM10 NC Pin Name Detailed Pin Descriptions Connect Pin Sysclk PinsCOREFB# Pins Pins FID30 Clock Multiplier Encodings FID30 Pins INIT# Pin Front-Side Bus Sense Truth TableFLUSH# Pin IGNNE# Pin NC Pins Jtag PinsK7CLKOUT# Pins Key Pins VID40 Pins SADDOUT10# PinsScan Pins Thermdc Pins VID40 ZN and ZP PinsVID40 Code to Voltage Definition Vrefsys Pin Standard AMD Athlon XP Processor Model 10 Products Ordering Information Preliminary Information Constants and Variables for the Ideal Diode Equation Ideal Diode Equation Temperature Offset Correction --- I-- high------  Preliminary Information Appendix B Signals and Bits Data Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning API Acronyms NMI VGA Related Publications Preliminary Information