Connect State, Diagram | AMD 10, 27493, 27488 specs

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C— May 2003

	Connect State	Figure 6 below and Figure 7 on page 17 show the Northbridge
	Diagram	and processor connect state diagrams, respectively.
			4/A
			2/A	1
			2/A
	Disconnect		Connect	Disconnect
		Pending	Connect	Requested
		Pending		Requested
			3/C	3
	5/B		8	8
	Disconnect		Reconnect	Probe
	Disconnect		Pending	Pending 2
			Pending	Pending 2

7/D,C

6/C	Probe	7/D
	Pending 1

	Condition

1	A disconnect is requested and probes are still pending.

2	A disconnect is requested and no probes are pending.

3	A Connect special cycle from the processor.

4	No probes are pending.

5	PROCRDY is deasserted.

6	A probe needs service.

7	PROCRDY is asserted.

	Three SYSCLK periods after CLKFWDRST is deasserted.
8	Although reconnected to the system interface, the
8	Northbridge must not issue any non-NOP SysDC
	commands for a minimum of four SYSCLK periods after
	deasserting CLKFWDRST.

		Action
	A	Deassert CONNECT eight SYSCLK periods
	A	after last SysDC sent.
		after last SysDC sent.

BAssert CLKFWDRST.

CAssert CONNECT.

DDeassert CLKFWDRST.

Figure 6. Northbridge Connect State Diagram

16

Power Management

Chapter 4

Image 28

AMD 10, 27493, 27488 manual Connect State, Diagram

Contents

Data Sheet 2002, 2003 Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information Preliminary Information Logic Symbol Diagram List of Figures Viii List of Tables List of Tables Revision History Date Rev, revised wording in the Overview May Xii Overview Delivering extreme performance for Windows XP QuantiSpeed Architecture Summary LAN Preliminary Information Signaling Technology Interface SignalsOverview AMD Athlon System Bus Signals Push-Pull PP Drivers Frequency Control Front-Side Bus Autodetect Legacy Logic Symbol DiagramDiode Preliminary Information Power Management Power Management States Working State Halt State Preliminary Information Probe State Connect and Disconnect ProtocolConnect Protocol Preliminary Information Procrdy Exiting the Stop Grant State and Bus Connect Sequence Diagram Connect State Connect Pending Disconnect Disconnect4/C Disconnect requestReturn internal clocks to full speed and assert Northbridge Clock Control Cpuid Support Preliminary Information Maximum Maximum Typical68.3 W 53.7 W 12.1 a Advanced 333 FSB Sysclk and SYSCLK# AC Characteristics Parameter Description Minimum MaximumClock Frequency Duty Cycle Advanced 333 FSB AMD Athlon System Bus AC Characteristics Advanced 333 FSB AMD Athlon System Bus DC Characteristics Advanced 333 FSB AMD Athlon System Bus DC Characteristics Maximum Typical 2100 3000+ 12.1 a 68.3 W 53.7 W2200 3200+ 76.8 W 60.4 W Advanced 400 FSB Sysclk and SYSCLK# AC Characteristics Advanced 400 FSB AMD Athlon System Bus AC Characteristics Advanced 400 FSB AMD Athlon System Bus DC Characteristics Advanced 400 FSB AMD Athlon System Bus DC Characteristics Interface Signal Groupings Interface Signal GroupingsElectrical Data Conventions VID40 DC Characteristics Voltage Identification VID40 Vcca AC and DC Characteristics FID30 DC CharacteristicsVcca AC and DC Characteristics Frequency Identification FID30 Vcccore Characteristics Vcccore AC and DC Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Signal Rise Time Signal Fall TimeInput Time to Acquire Input Time to Reacquire Open Drain Test Circuit 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Thermal Diode Characteristics CharacteristicsThermal Diode Electrical Characteristics Thermal Diode Guidelines for Platform Thermal Protection of the Processor Symbol Parameter Description Max Units500 Apic Pins AC and DC Characteristics Apic Pin AC and DC Characteristics Preliminary Information Signal and Power-Up Requirements Power-Up Requirements Pwrok Preliminary Information Clock Multiplier Processor Warm Reset RequirementsSelection FID30 Mechanical Data Die LoadingMechanical Loading Location Dynamic MAX Static MAX Units Die Surface 100 Letter or Minimum Maximum 453 Preliminary Information Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Preliminary Information Preliminary Information Pin Diagram and Pin Name Abbreviations Pin Descriptions AMD Athlon XP Processor Bottomside View Pin Name Abbreviations Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33 AA31AC31 AD30 AE33 AJ35AG37 AL33 W33 J35E27 E15 F24 F28F32 F34 AK34 AK36AM10 AM14 V30 V32V34 V36 Pin List Cross-Reference by Pin Location Pin NameNo Pin A35 SDATA40# A37 SDATA30# SDATA52# E11 SDATA50# E13 SDATA49# E15 E29 SDATA33# E31 SDATA32# Pin NameE33 NC Pin E35 SDATA31# E37 SDATA22# NC Pin F10 NC Pin H10 H12 H28 NC Pin H30 H32 H34NC Pin VID4 J31 J33 SDATA19# J35 J37 SDATA29# Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16# S31 NC Pin S33S35 SDATA15# S37 U31 NC Pin U33 FID0 FID1 NC Pin W31 W33FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 Y37 SDATA12# NC Pin AD30 AD32 AE31 NC Pin AE33NC Pin AF10 AF12 AF20 AH30 FSBSense1 AH32 NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21AJ27 NC Pin AJ29 NC Pin AK10 AL25 NC Pin AL27 AL29 NC Pin AM10NC Pin Name AN11 NC Pin AN13 Detailed Pin Descriptions Sysclk Pins COREFB# PinsPins Connect Pin FID30 Pins FID30 Clock Multiplier Encodings Front-Side Bus Sense Truth Table FLUSH# PinIGNNE# Pin INIT# Pin Jtag Pins K7CLKOUT# PinsKey Pins NC Pins SADDOUT10# Pins Scan PinsThermdc Pins VID40 Pins ZN and ZP Pins VID40 Code to Voltage DefinitionVrefsys Pin VID40 Ordering Information Standard AMD Athlon XP Processor Model 10 Products Preliminary Information Ideal Diode Equation Constants and Variables for the Ideal Diode Equation Temperature Offset Correction --- I-- high------  Preliminary Information Signals and Bits Appendix B Data Terminology Abbreviations Abbreviations and AcronymsAbbreviation Meaning Acronyms API NMI VGA Related Publications Preliminary Information