Test Circuit, Ordering Information | Cypress CY2291 manual

CY2291

Figure 5. CPU Frequency Change

SELECT

OLD SELECT

NEW SELECT STABLE

CPU

Fold

t8 & t10

Fnew

VDD

0.1 μF

VDD

0.1 μF

CLOAD

Note

16. Not recommended for new designs.

Document #: 38-07189 Rev. *C

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Contents

Benefits FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion Court Pinouts Pin Definitions Name Pin Number Description Custom Configuration Request Procedure Output ConfigurationPower Saving Features Operation Operating Conditions5 Electrical Characteristics, CommercialMaximum Ratings Parameter Description Part Numbers Min Max Unit Electrical Characteristics, Industrial Parameter Name Description Min Typ Max Unit Switching Characteristics, CommercialCpll 66.6 MHz 76.923 kHz Output Duty CY2291F MHzOperation 80 MHz 76.923 kHz CY2291F 50% 5V operation 90 MHz 76.923 kHz CY2291FI Switching Characteristics, IndustrialOutput Period Clock output range CY2291I 80 MHz 76.923 kHz Output Duty Clock Jitter14 Peak-to-peak period jitter Switching WaveformsMHz/ms Clock Jitter14 Peak-to-peak period jitter fOUT 50 MHz Test Circuit Package CharacteristicsOrdering Information Package Diagram Pin 300 MIL Soic Package Outline Document History Sales, Solutions, and Legal InformationOrig. Submission Description of Change Date