MoBL® CY62148EV30
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
tRC
ADDRESS
tAA
tOHA
DATA OUT | PREVIOUS DATA VALID |
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| DATA VALID |
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| Figure 2. Read Cycle No. 2 (OE Controlled) [17, 18] |
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ADDRESS |
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| tRC |
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CE |
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| tACE |
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OE |
| tHZOE |
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| tDOE |
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| tHZCE |
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| tLZOE | HIGH | |
| HIGH IMPEDANCE |
| IMPEDANCE |
DATA OUT | DATA VALID |
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tLZCE |
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| tPD |
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V | tPU | ICC | |
CC | 50% |
| 50% |
SUPPLY |
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CURRENT |
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| ISB |
| Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20] |
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| tWC |
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ADDRESS |
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| tSCE |
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CE |
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| tAW |
| tHA |
| tSA | tPWE |
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WE |
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OE |
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| tSD | t |
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| HD |
DATA IO | NOTE 21 | DATA VALID |
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| tHZOE |
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Notes
16.Device is continuously selected. OE, CE = VIL.
17.WE is HIGH for read cycles.
18.Address valid before or similar to CE transition LOW.
19.Data IO is high impedance if OE = VIH.
20.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
21.During this period, the IOs are in output state. Do not apply input signals.
Document #: | Page 6 of 12 |
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