Cypress CY62157CV30, CY62157CV33 CY62157CV30/33

CY62157CV30/33

Document #: 38-05014 Rev. *F Page 7 of 13

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[15, 16]

Read Cycle No. 2 (OE Controlled)[16, 17]

Notes:

15.Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH.

16.WE is HIGH for Read cycle.

17.Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

HIGH

CE1

ICC

ISB

IMPEDANCE

ADDRESS

CE2

DATA OUT

VCC

SUPPLY

CURRENT

BHE/BLE

tLZBE

tHZBE

[+] Feedback

Contents

Main 512K x 16 Static RAM CY62157CV30/33 Features Functional Description CY62157CV30/33 Product Portfolio VCC Range Product Range Pin Configurations CY62157CV30/33 Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance CY62157CV30/33 Capacitance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62157CV30/33 Switching Characteristics CY62157CV30/33 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[16, 17] Document #: 38-05014 Rev. *F Page 8 of 13 Write Cycle No. 1 (WE Controlled)[14, 18, 19] Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19] Write Cycle No. 3 (WE Controlled, OE LOW)[19] t Truth Table Typical DC and AC Characteristics Standby Current vs. Supply Voltage Access Time vs. Supply Voltage Operating Current vs. Supply Voltage Package Diagram Ordering Information Diagram Package Type Operating Speed (ns) Ordering Code Package 48-Ball (6 mm x 10 mm x 1.2 mm) FBGA (51-85128) Document History Page