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Cypress CY62157CV30, CY62157CV33 Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19], Write Cycle No. 3 (WE Controlled, OE LOW)[19], t

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CY62157CV30/33

Document #: 38-05014 Rev. *F Page 9 of 13

Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19]Write Cycle No. 3 (WE Controlled, OE LOW)[19]

Switching Waveforms (continued)

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

CE1

ADDRESS

CE2

DATA I/O

NOTE 20

BHE/BLE tBW

tSA

DATAIN VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

CE1

ADDRESS

CE2

DATAI/O NOTE 20

tBW

BHE/BLE

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Contents

Main 512K x 16 Static RAM CY62157CV30/33 Features Functional Description CY62157CV30/33 Product Portfolio VCC Range Product Range Pin Configurations CY62157CV30/33 Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance CY62157CV30/33 Capacitance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62157CV30/33 Switching Characteristics CY62157CV30/33 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[16, 17] Document #: 38-05014 Rev. *F Page 8 of 13 Write Cycle No. 1 (WE Controlled)[14, 18, 19] Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19] Write Cycle No. 3 (WE Controlled, OE LOW)[19] t Truth Table Typical DC and AC Characteristics Standby Current vs. Supply Voltage Access Time vs. Supply Voltage Operating Current vs. Supply Voltage Package Diagram Ordering Information Diagram Package Type Operating Speed (ns) Ordering Code Package 48-Ball (6 mm x 10 mm x 1.2 mm) FBGA (51-85128) Document History Page