Cypress CY62157EV18 CY62157EV18 MoBL

CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 2 of 12

Logic Block Diagram

Pin Configuration [3]

512K x 16

RAM Array IO0–IO7

ROW DECODER

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A3IO8–IO15

BLE

BHE

A16

A17

BHE

BLE

A10

A18

POWER DOWN

CIRCUIT CE2

CE1

CE2

CE1

Note

3. NC pins are not connected on the die.

A11

A10

A3CE1

IO10

IO8

IO9

IO11

IO13

IO12

IO14

IO15

VSS

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO3

IO4

IO5IO6

IO7

A15

A14

A13

A12

A18 NC

326

A16

VCC

VCC VSS

48-ball VFBGA

Top Vie w

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Contents

Main CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM Features Functional Description Product Portfolio CY62157EV18 MoBL Document #: 38-05490 Rev. *D Page 2 of 12 Logic Block Diagram Pin Configuration 48-ball VFBGA Top Vie w Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62157EV18 MoBL Switching Characteristics CY62157EV18 MoBL Switching Waveforms Read Cycle 2 (OE Controlled) [18, 19] Read Cycle 1 (Address Transition Controlled) [17, 18] CY62157EV18 MoBL Write Cycle 1 (WE Controlled) [16, 20, 21] Write Cycle 2 (CE1 or CE2 Controlled) [16, 20, 21] Switching Waveforms CY62157EV18 MoBL Document #: 38-05490 Rev. *D Page 8 of 12 Write Cycle 3 (WE Controlled, OE LOW) [21] t Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21] Truth Table Ordering Information Package Diagrams Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150-*D Document History