Cypress CY62157EV18 CY62157EV18 MoBL

CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 7 of 12

Write Cycle 1 (WE Controlled) [16, 20, 21]

Write Cycle 2 (CE1 or CE2 Controlled) [16, 20, 21]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID D ATA

tBW

NOTE 22

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 22

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

Notes:

20.Data IO is high impedance if OE = VIH.

21.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

22.During this period, the IOs are in output state and input signals must not be applied.

[+] Feedback

Contents

Main CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM Features Functional Description Product Portfolio CY62157EV18 MoBL Document #: 38-05490 Rev. *D Page 2 of 12 Logic Block Diagram Pin Configuration 48-ball VFBGA Top Vie w Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62157EV18 MoBL Switching Characteristics CY62157EV18 MoBL Switching Waveforms Read Cycle 2 (OE Controlled) [18, 19] Read Cycle 1 (Address Transition Controlled) [17, 18] CY62157EV18 MoBL Write Cycle 1 (WE Controlled) [16, 20, 21] Write Cycle 2 (CE1 or CE2 Controlled) [16, 20, 21] Switching Waveforms CY62157EV18 MoBL Document #: 38-05490 Rev. *D Page 8 of 12 Write Cycle 3 (WE Controlled, OE LOW) [21] t Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21] Truth Table Ordering Information Package Diagrams Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150-*D Document History