Write Cycle No WE Controlled18, 22 | Cypress CY62157EV30 specs

CY62157EV30 MoBL®

Switching Waveforms (continued)

Write Cycle No. 1 (WE Controlled)[18, 22, 23]

Figure 5. Write Cycle No. 1

		tWC
ADDRESS
		tSCE
CE1
CE2
	tAW	tHA
WE	tSA	tPWE
WE
BHE/BLE		tBW
BHE/BLE
OE		tHD
		tSD
DATA IO	NOTE 24	VALID DATA
	tHZOE

Write Cycle No. 2 (CE1 or CE2 Controlled)[18, 22, 23]

Figure 6. Write Cycle No. 1

		tWC
ADDRESS
		tSCE
CE1
CE2
	tSA	tHA
	tAW	tHA
WE		tPWE
WE
BHE/BLE		tBW
BHE/BLE
OE		tHD
		tSD
DATA IO	NOTE 24	VALID DATA
	tHZOE

Notes

22.Data IO is high impedance if OE = VIH.

23.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

24.During this period, the IOs are in output state. Do not apply input signals.

Document #: 38-05445 Rev. *E

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Cypress CY62157EV30 manual Write Cycle No WE Controlled18, 22, Write Cycle No CE1 or CE2 Controlled18, 22

Contents

Features Logic Block DiagramFunctional Description1 Cypress Semiconductor Corporation Pin Configuration Product Portfolio Following picture shows the 48-ball Vfbga pinout.3, 4 Ball Vfbga Top View Electrical Characteristics Maximum RatingsOperating Range Capacitance Data Retention Characteristics Thermal ResistanceAC Test Loads and Waveforms Data Retention Waveform12 Switching Characteristics Write Cycle Switching Waveforms Read Cycle No Address Transition Controlled19 Write Cycle No WE Controlled18, 22 Write Cycle No CE1 or CE2 Controlled18, 22 Write Cycle No WE Controlled, OE LOW23 Write Cycle No BHE/BLE Controlled, OE LOW23 Inputs/Outputs Mode Power Truth TableOrdering Information BHE BLE Package Diagrams Pin Vfbga 6 x 8 x 1 mm Pin Tsop II Pin Tsop I 12 mm x 18.4 mm x 1.0 mm Issue Date Orig. Change Description of Change Document HistoryDocument Number REV ECN no