Cypress CY62157EV30 manual Switching Characteristics, Write Cycle

CY62157EV30 MoBL®

Switching Characteristics

Over the Operating Range[13, 14]

Parameter						Description	45 ns (Ind’l/Auto-A)		Unit
							Min	Max
Read Cycle
tRC	Read Cycle Time						45		ns
tAA	Address to Data Valid							45	ns
tOHA	Data Hold from Address Change						10		ns
tACE		1 LOW and CE2 HIGH to Data Valid						45	ns
	CE
tDOE			LOW to Data Valid					22	ns
	OE
tLZOE			LOW to LOW-Z[15]				5		ns
	OE
tHZOE			HIGH to High-Z[15, 16]					18	ns
	OE
tLZCE		1 LOW and CE2 HIGH to Low-Z[15]					10		ns
	CE
t				HIGH and CE		LOW to High-Z[15, 16]		18	ns
	CE	1			2
HZCE
tPU		1 LOW and CE2 HIGH to Power Up					0		ns
	CE
tPD		1 HIGH and CE2 LOW to Power Down						45	ns
	CE
tDBE								45	ns
	BLE/BHE LOW to Data Valid
t							5		ns
	BLE/BHE LOW to Low-Z[15, 17]
LZBE
t								18	ns
	BLE/BHE HIGH to HIGH-Z[15, 16]
HZBE
Write Cycle[18]
tWC	Write Cycle Time						45		ns
tSCE		1 LOW and CE2 HIGH to Write End					35		ns
	CE
tAW	Address Setup to Write End						35		ns
tHA	Address Hold from Write End						0		ns
tSA	Address Setup to Write Start						0		ns
tPWE			Pulse Width				35		ns
	WE
tBW							35		ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End						25		ns
tHD	Data Hold from Write End						0		ns
t			LOW to High-Z[15, 16]					18	ns
	WE
HZWE
tLZWE			HIGH to Low-Z[15]				10		ns
	WE

Notes

13.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.

14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

15.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

17.If both byte enables are toggled together, this value is 10 ns.

18.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 38-05445 Rev. *E Page 6 of 14

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