Read/Write Cycle Timing16, 18, Clz | Cypress CY7C1215H specification

CY7C1215H

Switching Waveforms (continued)

Read/Write Cycle Timing[16, 18, 19]

			tCYC
CLK
		tCH	tCL
	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2
BWE,
BW[A:D]
	tCES	tCEH
CE
ADV
OE
			tCO

A3 A4

tWES tWEH

tDS tDH

A5 A6

Data In (D)	High-Z	t	tOEHZ
		t	tOEHZ
		CLZ
Data Out (Q)	High-Z	Q(A1)	Q(A2)

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

19.GW is HIGH.

Document #: 38-05666 Rev. *B

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Cypress CY7C1215H manual Read/Write Cycle Timing16, 18, Clz

Contents

Features Logic Block DiagramFunctional Description1 Cypress Semiconductor Corporation Pin Configuration Pin Tqfp Selection GuideCY7C1215H 166 MHz 133 MHz Unit Pin Definitions Sleep Mode Functional OverviewBurst Sequences Interleaved Burst Address Table Mode = Floating or VDD First Second Third Fourth Address A1, A0Next Cycle Add. Used Adsp Adsc ADV Truth Table for Read/Write2 FunctionBWE BW D BW C BW B BW a Electrical Characteristics Over the Operating Range7 Maximum RatingsOperating Range Ambient Range Capacitance9 Thermal Resistance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 Switching Waveforms Read Cycle Timing16 Write Cycle Timing16 Read/Write Cycle Timing16, 18 CLZ ZZ Mode Timing20 DON’T Care Package Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryREV ECN no