1-Mbit (32K x 32) Pipelined Sync SRAM

CY7C1215H

CypressSemiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05666 Rev. *B Revised July 5, 2006

Features

• Registered inputs and outputs for pipelined operation
• 32K × 32 common I/O architecture
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1215H SRAM integrates 32K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1215H operates from a +3.3V core power supply
while all outputs may operate either with a + 2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Logic Block Diagram

ADDRESS
REGISTER
ADV
CLK BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A
0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRAY
DQ
s
SLEEP
CONTROL
ZZ
A[1:0]
2
DQA
BYTE
WRITE REGISTER
DQB
BYTE
WRITE REGISTER
DQC
BYTE
WRITE REGISTER
DQD
BYTE
WRITE REGISTER
DQA
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQD
BYTE
WRITE DRIVER
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