Cypress CY7C1215H manual Document History, REV ECN no, Issue Date Orig. Description of Change

Models: CY7C1215H

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CY7C1215H

Document Title: CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM

Document Number: 38-05666

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	343896	See ECN	PCI	New Data Sheet

*A	430678	See ECN	NXR	Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Added 2.5VI/O option
				Changed Three-State to Tri-State
				Included Maximum Ratings for VDDQ relative to GND
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table
				Modified test condition from VIH < VDD to VIH < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table
*B	481916	See ECN	VKN	Converted from Preliminary to Final.
				Updated the Ordering Information table.

Document #: 38-05666 Rev. *B

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1166 MHz 133 MHz Unit Pin Configuration Pin TqfpSelection Guide CY7C1215HPin Definitions Sleep Mode Functional OverviewBurst Sequences Adsp Adsc ADV Interleaved Burst Address Table Mode = Floating or VDDFirst Second Third Fourth Address A1, A0 Next Cycle Add. UsedTruth Table for Read/Write2 FunctionBWE BW D BW C BW B BW a Ambient Range Electrical Characteristics Over the Operating Range7Maximum Ratings Operating RangeCapacitance9 Thermal Resistance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 Read Cycle Timing16 Switching WaveformsWrite Cycle Timing16 CLZ Read/Write Cycle Timing16, 18DON’T Care ZZ Mode Timing20Package Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryREV ECN no