Cypress CY7C1316BV18, CY7C1318BV18, CY7C1320BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18

CY7C1316BV18, CY7C1916BV18
CY7C1318BV18, CY7C1320BV18
Document Number: 38-05621 Rev. *D Page 2 of 31
Logic Block Diagram (CY7C1316BV18)
Logic Block Diagram (CY7C1916BV18)
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
Write Add. Decode
8
20
C
C
8
LD
Control
R/W
DOFF
1M x 8 Array
1M x 8 Array
8
DQ[7:0]
8
CQ
CQ
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
Write Add. Decode
9
20
C
C
9
LD
Control
R/W
DOFF
1M x 9 Array
1M x 9 Array
9
DQ[8:0]
9
CQ
CQ
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