Contents
Main
18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
Features
Configurations
Functional Description
CY7C1318BV18, CY7C1320BV18
Document Number: 38-05621 Rev. *D Page 2 of 31
Logic Block Diagram (CY7C1316BV18)
Logic Block Diagram (CY7C1916BV18)
1M x 8 Array 1M x 8 Array
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
Document Number: 38-05621 Rev. *D Page 3 of 31
Logic Block Diagram (CY7C1318BV18)
Logic Block Diagram (CY7C1320BV18)
512K x 18 Array 512K x 18 Array
Pin Configuration
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
Pin Configuration
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1316BV18, CY7C1916BV18
Pin Definitions
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
Pin Definitions
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
Functional Overview
Read Operations
Write Operations
Byte Write Operations
CY7C1316BV18, CY7C1916BV18
Programmable Impedance
SRAM#1 SRAM#2
Echo Clocks
DLL
Truth Table
Burst Address Table
Page
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access PortTest Clock
Test Mode Select (TMS)
Test D ata- In (T DI)
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
TAP Controller State Diagram
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1316BV18, CY7C1916BV18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Identification Register Definitions
Scan Register Sizes
Instruction Codes
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
Boundary Scan Order
CY7C1316BV18, CY7C1916BV18
Power Up Sequence in DDR-II SRAM
VV
Power Up Sequence
DLL Constraints
CY7C1318BV18, CY7C1320BV18
Maximum Ratings
Operating Range
Electrical Characteristics
DC Electrical Characteristics
Electrical Characteristics
DC Electrical Characteristics
Capacitance
Thermal Resistance
Page
Switching Characteristics
Document Number: 38-05621 Rev. *D Page 25 of 31
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence
READ READREAD NOP NOP WRITEWRITE NOP 12345678910
Page
Page
Ordering Information
Document Number: 38-05621 Rev. *D Page 29 of 31
Package Diagram
[+] Feedback
SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
1.40MAX.
Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
Document History Page
CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18
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