CY7C1316BV18, CY7C1916BV18

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18, CY7C1320BV18

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

 

 

 

Pin Description

 

CQ

Output Clock

 

CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

 

 

 

 

 

 

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

 

 

 

 

 

 

the echo clocks is shown in Switching Characteristics on page 23.

 

 

 

 

Output Clock

 

 

Referenced with Respect to

 

. This is a free running clock and is synchronized to the input clock

 

CQ

 

 

 

CQ

C

 

 

 

 

 

 

for output data

(C)

of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

 

 

 

 

 

 

the echo clocks is shown in Switching Characteristics on page 23.

 

ZQ

Input

 

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

 

 

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

 

 

between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the

 

 

 

 

 

 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

 

 

 

Input

 

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

 

DOFF

 

 

 

 

 

 

in the DLL turned off operation is different from that listed in this data sheet.

 

TDO

Output

 

TDO for JTAG.

 

 

 

 

 

 

TCK

Input

 

TCK Pin for JTAG.

 

 

 

 

 

 

TDI

Input

 

TDI Pin for JTAG.

 

 

 

 

 

 

TMS

Input

 

TMS Pin for JTAG.

 

 

 

 

 

 

NC

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

NC/36M

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

NC/72M

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

NC/144M

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

NC/288M

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

VREF

Input-

 

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

 

 

 

 

Reference

 

measurement points.

 

VDD

Power Supply

 

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

 

Ground for the Device.

 

VDDQ

Power Supply

 

Power Supply Inputs for the Outputs of the Device.

Document Number: 38-05621 Rev. *D

Page 7 of 31

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Cypress CY7C1916BV18 manual Referenced with Respect to, TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag
Page 6 Page 8

CY7C1316BV18, CY7C1916BV18, CY7C1320BV18, CY7C1318BV18 specifications

The Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 are advanced synchronous static RAM (SRAM) devices designed to meet the high-performance requirements of modern computing systems. Offering a blend of high speed, low power consumption, and large storage capacities, these chips are widely utilized in applications such as networking equipment, telecommunications, and high-speed data processing.

The CY7C1318BV18 is a 2 Megabit SRAM that operates at a 2.5V supply voltage. It features a fast access time of 10ns, making it an excellent choice for systems that require rapid data retrieval. Its asynchronous interface simplifies integration into a wide range of devices. In terms of power efficiency, the CY7C1318BV18 has a low operating current, ensuring that it can be utilized in battery-powered applications without significantly draining power.

Similarly, the CY7C1320BV18 offers a larger 256 Kbit capacity while maintaining the same low-voltage operation and performance characteristics. This chip also features a synchronous interface, supporting high-speed data transfer rates that are ideal for networking and communication devices. The CY7C1320BV18's features include deep-write operation capabilities, enhancing its performance in write-intensive applications.

The CY7C1916BV18 takes performance a step further with its 32 Megabit capacity, suitable for applications requiring extensive memory resources. This device also supports advanced functions such as burst read modes, allowing for faster sequential data access. With its low-latency performance, the CY7C1916BV18 is an excellent choice for applications like digital signal processing and real-time data analysis.

Lastly, the CY7C1316BV18 is another variant offering 1 Megabit of storage. It combines high-speed functionality with low power usage, supporting a wide range of applications including consumer electronics and automotive systems. Its robust design ensures reliability under varying environmental conditions.

All of these SRAM devices incorporate Cypress’s advanced semiconductor technology, providing a combination of speed, efficiency, and reliability. They are available in various package options, which facilitate easy integration into diverse system designs. Overall, the Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 exemplify the company’s commitment to delivering high-quality memory solutions that cater to the evolving needs of the electronic industry.
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