Referenced with Respect to, TDO for Jtag | Cypress CY7C1916BV18, CY7C1318BV18

CY7C1316BV18, CY7C1916BV18

Pin Description

Output Clock

CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 23.

Output Clock

Referenced with Respect to

. This is a free running clock and is synchronized to the input clock

for output data

(C)

of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 23.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

DOFF

in the DLL turned off operation is different from that listed in this data sheet.

TDO

Output

TCK

Input

TDI

Input

TMS

Input