CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Capacitance
This parameter is guaranteed but not tested.
Parameter | Description | Test Conditions | Max | Unit |
CIN | Input Capacitance | TA = 25°C, f = 1 MHz, VCC = 5.0V | 15 | pF |
COUT | Output Capacitance |
| 10 | pF |
Figure 3. AC Test Loads and Waveforms
5V | R1 893Ω |
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5V | R1 893Ω |
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5V
OUTPUT |
30 pF |
| R2 |
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| 347Ω |
INCLUDING
OUTPUT |
5 pF |
| R2 |
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| 347Ω |
INCLUDING
BUSY OR 
INT
281Ω
30 pF
JIG AND SCOPE (a)
JIG AND SCOPE (b)
BUSY Output Load (CY7C132/CY7C136 Only)
Equivalent to: | THÉVENIN EQUIVALENT | 3.0V |
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| 250Ω |
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OUTPUT |
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| 1.4V | GND |
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< 5 ns 
ALL INPUT PULSES
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| < 5 ns |
Switching Characteristics
Over the Operating Range (Speeds
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| Min | Max | Min | Max | Min | Max |
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Read Cycle |
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tRC |
| Read Cycle Time | 15 |
| 25 |
| 30 |
| ns | ||
tAA |
| Address to Data Valid [9] |
| 15 |
| 25 |
| 30 | ns | ||
tOHA |
| Data Hold from Address Change | 0 |
| 0 |
| 0 |
| ns | ||
tACE |
| CE |
| LOW to Data Valid [9] |
| 15 |
| 25 |
| 30 | ns |
tDOE |
| OE | LOW to Data Valid [9] |
| 10 |
| 15 |
| 20 | ns | |
tLZOE |
| OE | LOW to Low Z [7, 10] | 3 |
| 3 |
| 3 |
| ns | |
tHZOE |
| OE | HIGH to High Z [7, 10, 11] |
| 10 |
| 15 |
| 15 | ns | |
tLZCE |
| CE | LOW to Low Z [7, 10] | 3 |
| 5 |
| 5 |
| ns | |
tHZCE |
| CE | HIGH to High Z [7, 10, 11] |
| 10 |
| 15 |
| 15 | ns | |
tPU |
| CE | LOW to Power Up [7] | 0 |
| 0 |
| 0 |
| ns | |
tPD |
| CE | HIGH to Power Down [7] |
| 15 |
| 25 |
| 25 | ns | |
Shaded areas contain preliminary information.
Notes
8.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30 pF load capacitance.
9.AC test conditions use VOH = 1.6V and VOL = 1.4V.
10.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
11.tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady state voltage.
Document #: | Page 4 of 15 |
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