Cypress CY7C1320CV18-267BZXC Logic Block Diagram CY7C1318CV18, Logic Block Diagram CY7C1320CV18

CY7C1318CV18

CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

			A0			Burst
						Logic
	20				19
A(19:0)				A(19:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[1:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
	512Kx18Array	512Kx18Array		Logic	18
				Output	R/W
	Read Data Reg.			Control	C
					C

36
	18	Reg.		Reg.	18		CQ
							CQ
18						18
		Reg.	18				DQ[17:0]

Logic Block Diagram (CY7C1320CV18)

			A0			Burst
						Logic
	19				18
A(18:0)				A(18:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[3:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
	256Kx36Array	256Kx36Array		Logic	36
				Output	R/W
	Read Data Reg.			Control	C
					C

72
	36	Reg.		Reg.	36		CQ
							CQ
36						36
		Reg.	36				DQ[35:0]

Document Number: 001-07160 Rev. *F Page 2 of 26

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