Cypress CY7C1318CV18 CY7C1320CV18

CY7C1318CV18
CY7C1320CV18
Document Number: 001-07160 Rev. *F Page 8 of 26
Truth Table
The truth table for the CY7C1318CV18, and CY7C1320CV18 follows.[2, 3, 4, 5, 6, 7]
Operation KLD R/W DQ DQ
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H L L D(A1) at K(t + 1) ↑D(A2) at K(t + 1) ↑
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L-H L H Q(A1) at C(t + 1)↑Q(A2) at C(t + 2) ↑
NOP: No Operation L-H H X High-Z High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Burst Address Table
(CY7C1318CV18, CY7C1320CV18)
First Address (External) Second Address (Internal)
X..X0 X..X1
X..X1 X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1318CV18 follows. [2, 8]
BWS0BWS1KKComments
L L L–H – During the data portion of a write sequence :
Both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence :
Both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence :
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence :
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence :
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence :
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1318CV18 and CY7C1320CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
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