Cypress CY7C1320CV18-250BZXC, 001-07160 manual Power Up Sequence in DDR II Sram, DLL Constraints

CY7C1318CV18

CY7C1320CV18

Power Up Sequence in DDR II SRAM DLL Constraints

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

❐Drive DOFF HIGH.

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency.

■Provide stable DOFF (HIGH), power, and clock (K, K) for 1024 cycles to lock the DLL.

Figure 3. Power Up Waveforms

~ ~

K

K

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ VDDQ VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to VDDQ)

DOFF

Document Number: 001-07160 Rev. *F Page 17 of 26

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