CY7C1318CV18
CY7C1320CV18
Document Number: 001-07160 Rev. *F Page 20 of 26

Switching Characteristics

Over the Operating Range[20, 21]
Cypress
Parameter
Consortium
Parameter Description
267 MHz 250 MHz 200 MHz 167 MHz
Unit
Min Max Min Max Min Max Min Max
tPOWER VDD(Typical) to the First Access [22] 1–1–1–1–ms
tCYC tKHKH K Clock and C Clock Cycle Time 3.75 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 1.5 – 1.6 – 2.0 – 2.4 – ns
tKL tKLKH Input Clock (K/K and C/C) LOW 1.5 – 1.6 – 2.0 – 2.4 – ns
tKHKHtKHKHK Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
1.68 – 1.8 – 2.2 – 2.7 – ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
0.00 1.68 0.00 1.8 0.00 2.2 0.00 2.7 ns
Setup Times
tSA tAVKH Address Setup to K Clock Rise 0.3 – 0.5 – 0.6 – 0.7 – ns
tSC tIVKH Control Setup to K Clock Rise (LD, R/W) 0.3 – 0.5 – 0.6 – 0.7 – ns
tSCDDR tIVKH Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.3 – 0.35 – 0.4 – 0.5 – ns
tSD tDVKH D[X:0] Setup to Clock (K and K) Rise 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.3 – 0.5 – 0.6 – 0.7 – ns
tHC tKHIX Control Hold after K Clock Rise (LD, R/W) 0.3 – 0.5 – 0.6 – 0.7 – ns
tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.3 – 0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.3 – 0.35 – 0.4 – 0.5 – ns
Notes
21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.
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