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Cypress CY7C1320CV18-250BZXC TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Models: CY7C1320CV18-167BZC CY7C1318CV18-200BZI CY7C1318CV18-267BZXC CY7C1320CV18-250BZXC CY7C1320CV18-267BZXC CY7C1318CV18-250BZC CY7C1318CV18-200BZXC CY7C1320CV18-200BZC CY7C1318CV18-167BZC CY7C1320CV18-250BZC 001-07160 CY7C1318CV18-250BZXC

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						CY7C1318CV18
						CY7C1320CV18

Pin Definitions (continued)

	Pin Name		I/O			Pin Description
			Input	DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
	DOFF
				in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this
				pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I
				mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
				MHz with DDR I timing.
	TDO		Output	TDO for JTAG.

	TCK		Input	TCK Pin for JTAG.

	TDI		Input	TDI Pin for JTAG.

	TMS		Input	TMS Pin for JTAG.

	NC		N/A	Not Connected to the Die. Can be tied to any voltage level.

	NC/36M		N/A	Not Connected to the Die. Can be tied to any voltage level.

	NC/72M		N/A	Not Connected to the Die. Can be tied to any voltage level.

	NC/144M		N/A	Not Connected to the Die. Can be tied to any voltage level.

	NC/288M		N/A	Not Connected to the Die. Can be tied to any voltage level.

	VREF		Input-	Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
			Reference	measurement points.
	VDD		Power Supply	Power Supply Inputs to the Core of the Device.
	VSS		Ground	Ground for the Device.
	VDDQ		Power Supply	Power Supply Inputs for the Outputs of the Device.

Document Number: 001-07160 Rev. *F

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Cypress CY7C1320CV18-250BZXC TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag, Ground for the Device

Contents

Configurations FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1318CV18 1M x CY7C1320CV18 512K x Pin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Programmable Impedance Application ExampleEcho Clocks SRAM#1 ZQ Operation Write Cycle DescriptionsFirst Address External Second Address Internal Comments Device Write cycle description table for CY7C1320CV18 follows.2Into the device. D359 remains unaltered Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit Size Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in DDR II SramPower Up Sequence Electrical Characteristics Neutron Soft Error ImmunityDC Electrical Characteristics Maximum Ratings Capacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max Unit Parameter Min Max DLL Timing Parameter Min Max Output Times Read/Write/Deselect Sequence26, 27 Switching Waveforms CY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Ball Fbga 13 x 15 x 1.4 mm Package Diagram Document History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information