Cypress CY7C1318CV18-250BZC Application Example, Programmable Impedance, Echo Clocks, SRAM#1 ZQ

CY7C1318CV18

CY7C1320CV18

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR II to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchro- nized to the output clock of the DDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 20.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII™/DDRII.

Application Example

Figure 1 shows two DDR II used in an application.

Figure 1. Application Example

SRAM#1 ZQ

DQCQ/CQ#

A LD# R/W# C C# K K#

	DQ
BUS	Addresses
MASTER	Cycle Start#
(CPU	R/W#
or	Return CLK	Vterm = 0.75V
ASIC)	Source CLK
		R = 50ohms
	Return CLK#
		Vterm = 0.75V
	Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2

R = 250ohms	SRAM#2		ZQ
	DQ	CQ/CQ#
	A LD# R/W# C C#	K K#

R = 250ohms

Document Number: 001-07160 Rev. *F Page 7 of 26

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