Cypress manual PRELIMINARYCY7C1336H, Features, Functional Description1, Logic Block Diagram

PRELIMINARYCY7C1336H

2-Mbit (64K x 32) Flow-Through Sync SRAM

Features

•64K x 32 common I/O

•3.3V core power supply

•3.3V I/O supply

•Fast clock-to-output times

—6.5 ns (133-MHz version)

—8.0 ns (100-MHz version)

•Provide high-performance 2-1-1-1 access rate

•User-selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Supports 3.3V I/O level

•Offered in JEDEC-standard lead-free 100-pin TQFP package

•“ZZ” Sleep Mode option

Functional Description[1]

The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is

6.5ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1336H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1336H operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram		ADDRESS
A0, A1, A
		REGISTER
MODE			A[1:0]
ADV		BURST	Q1
CLK		COUNTER
		AND LOGIC
		CLR	Q0
ADSC
ADSP
		DQD	DQD
BWD			BYTE
		BYTE
			WRITE REGISTER
		WRITE REGISTER
		DQC	DQC
BWC			BYTE
		BYTE
			WRITE REGISTER
		WRITE REGISTER		MEMORY		OUTPUT	DQs
					SENSE
				ARRAY		BUFFERS
			DQB		AMPS
		DQB
BWB			BYTE
		BYTE	WRITE REGISTER
		WRITE REGISTER
			DQA
BWA		DQA	BYTE
		BYTE	WRITE REGISTER
BWE
		WRITE REGISTER
GW						INPUT
CE1		ENABLE				REGISTERS
		REGISTER
CE2
CE3
OE
ZZ	SLEEP
	CONTROL
Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-00210 Rev. *A		Revised February 6, 2006

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