PRELIMINARY

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1336H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ Mode Electrical Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

Description

 

 

 

 

 

 

Test Conditions

 

 

 

Min.

 

 

 

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDDZZ

Sleep mode standby current

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

40

 

mA

 

tZZS

Device operation to ZZ

 

 

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

2tCYC

ns

 

tZZREC

ZZ recovery time

 

 

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

 

 

2tCYC

 

 

 

 

 

ns

 

tZZI

ZZ Active to sleep current

 

 

 

 

This parameter is sampled

 

 

 

 

 

 

2tCYC

ns

 

tRZZI

ZZ Inactive to exit sleep current

 

 

 

 

This parameter is sampled

0

 

 

 

 

 

 

 

ns

 

Truth Table [2, 3, 4, 5, 6]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Description

 

Used

 

CE1

 

CE2

 

CE3

ZZ

ADSP

 

 

ADSC

 

ADV

 

WRITE

 

OE

 

CLK

 

DQ

 

Deselected Cycle,

 

None

 

H

 

X

 

X

L

 

X

 

 

L

 

X

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

 

None

 

L

 

L

 

X

L

 

L

 

 

X

 

X

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

 

None

 

L

 

X

 

H

L

 

L

 

 

X

 

X

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

 

None

 

L

 

L

 

X

L

 

H

 

 

L

 

X

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

 

None

 

X

 

X

 

X

L

 

H

 

 

L

 

X

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power-down

 

None

 

X

 

X

 

X

H

 

X

 

 

X

 

X

 

X

 

X

 

X

 

Tri-State

 

Read Cycle, Begin Burst

 

External

 

L

 

H

 

L

L

 

L

 

 

X

 

X

 

X

 

L

 

L-H

 

Q

 

Read Cycle, Begin Burst

 

External

 

L

 

H

 

L

L

 

L

 

 

X

 

X

 

X

 

H

 

L-H

 

Tri-State

 

Write Cycle, Begin Burst

 

External

 

L

 

H

 

L

L

 

H

 

 

L

 

X

 

L

 

X

 

L-H

 

D

 

Read Cycle, Begin Burst

 

External

 

L

 

H

 

L

L

 

H

 

 

L

 

X

 

H

 

L

 

L-H

 

Q

 

Read Cycle, Begin Burst

 

External

 

L

 

H

 

L

L

 

H

 

 

L

 

X

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Continue Burst

 

Next

 

X

 

X

 

X

L

 

H

 

 

H

 

L

 

H

 

L

 

L-H

 

Q

 

Read Cycle, Continue Burst

 

Next

 

X

 

X

 

X

L

 

H

 

 

H

 

L

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Continue Burst

 

Next

 

H

 

X

 

X

L

 

X

 

 

H

 

L

 

H

 

L

 

L-H

 

Q

 

Read Cycle, Continue Burst

 

Next

 

H

 

X

 

X

L

 

X

 

 

H

 

L

 

H

 

H

 

L-H

 

Tri-State

 

Write Cycle, Continue Burst

 

Next

 

X

 

X

 

X

L

 

H

 

 

H

 

L

 

L

 

X

 

L-H

 

D

 

Write Cycle, Continue Burst

 

Next

 

H

 

X

 

X

L

 

X

 

 

H

 

L

 

L

 

X

 

L-H

 

D

 

Read Cycle, Suspend Burst

 

Current

 

X

 

X

 

X

L

 

H

 

 

H

 

H

 

H

 

L

 

L-H

 

Q

 

Read Cycle, Suspend Burst

 

Current

 

X

 

X

 

X

L

 

H

 

 

H

 

H

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Suspend Burst

 

Current

 

H

 

X

 

X

L

 

X

 

 

H

 

H

 

H

 

L

 

L-H

 

Q

 

Read Cycle, Suspend Burst

 

Current

 

H

 

X

 

X

L

 

X

 

 

H

 

H

 

H

 

H

 

L-H

 

Tri-State

 

Write Cycle, Suspend Burst

 

Current

 

X

 

X

 

X

L

 

H

 

 

H

 

H

 

L

 

X

 

L-H

 

D

 

Write Cycle, Suspend Burst

 

Current

 

H

 

X

 

X

L

 

X

 

 

H

 

H

 

L

 

X

 

L-H

 

D

 

Notes:

2.X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3.WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H.

4.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5.The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle.

6.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 001-00210 Rev. *A

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Cypress CY7C1336H manual ZZ Mode Electrical Characteristics, Parameter Description Test Conditions Min Max Unit, Address
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CY7C1336H specifications

The Cypress CY7C1336H is a high-performance static random-access memory (SRAM) device that has gained recognition for its outstanding speed and reliability. This component is widely used in various high-performance applications including networking, telecommunications, and industrial control systems, where fast data storage and retrieval are critical.

One of the main features of the CY7C1336H is its high-speed operation, offering access times of as low as 10 nanoseconds. This makes it ideal for applications that require quick response times and efficient processing. The device operates with a supply voltage of 2.5V, which not only helps in reducing power consumption but also enables its use in newer low-voltage systems.

The CY7C1336H boasts a capacity of 1 megabit, organized in a configuration of 128K words by 8 bits. This allows it to store a significant amount of data while maintaining a compact footprint. In addition to its size, the device supports a burst mode, which enhances its efficiency in handling data transfer operations. This feature is particularly useful in applications requiring continuous data streaming, such as video processing or high-speed networking.

The memory technology employed in the CY7C1336H is known for its robustness and durability. Unlike DRAM, SRAM does not require periodic refreshing, which simplifies system design and improves overall performance. The device also features fast output enable and chip enable options, providing greater flexibility in controlling memory access and improving overall system response time.

In terms of packaging, the CY7C1336H is available in various forms including 32-pin SOJ and 44-pin TSOP packages, catering to diverse design requirements. Its compact packaging and low thermal characteristics make it suitable for space-constrained applications.

Another noteworthy characteristic of this SRAM is its inherent data integrity and reliability. With features such as on-chip parity generation and error checking capabilities, the CY7C1336H ensures that the data stored remains accurate and consistent over time.

Overall, the Cypress CY7C1336H delivers a blend of high speed, low power consumption, and reliability, making it an excellent choice for designers looking to implement high-performance memory solutions in their applications. Its combination of lasting performance and advanced features secures its place in both current and future electronic designs.
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