Cypress PRELIMINARYCY7C1336H, Timing Diagrams continued, Read/Write Timing16, 18, + Feedback

Models: CY7C1336H

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PRELIMINARYCY7C1336H

Timing Diagrams (continued)

tCYC

CLK

CH CL

tADS tADH

ADSP

ADSC

tAS tAH

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

A5 A6

D(A5) D(A6)

Back-to-Back WRITEs

Document #: 001-00210 Rev. *A

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Contents

Features Logic Block DiagramPRELIMINARYCY7C1336H Functional Description1Pin Configuration PRELIMINARYCY7C1336H Selection GuidePin Definitions PRELIMINARYCY7C1336H Interleaved Burst Address Table MODE = Floating or VDD Linear Burst Address Table MODE = GNDFunctional Overview PRELIMINARYCY7C1336HZZ Mode Electrical Characteristics PRELIMINARYCY7C1336H Truth Table for Read/Write 2 PRELIMINARYCY7C1336H Maximum Ratings Operating RangeElectrical Characteristics Over the Operating Range 7 PRELIMINARYCY7C1336HCapacitance9 Thermal Resistance9AC Test Loads and Waveforms PRELIMINARYSwitching Characteristics Over the Operating Range 10 CY7C1336HPRELIMINARY Timing Diagrams PRELIMINARYCY7C1336HRead Cycle Timing16 + FeedbackTiming Diagrams continued PRELIMINARYCY7C1336HWrite Cycle Timing16 + FeedbackTiming Diagrams continued PRELIMINARYCY7C1336HRead/Write Timing16, 18 + FeedbackTiming Diagrams continued ZZ Mode Timing2021. DQs are in High-Z when exiting ZZ sleep mode PRELIMINARYCY7C1336HPackage Diagram Ordering InformationPRELIMINARY CY7C1336HDocument History Page Issue DatePRELIMINARY CY7C1336H