CY7C138, CY7C139

4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

Features

■True Dual-Ported memory cells that enable simultaneous reads of the same memory location

■4K x 8 organization (CY7C138)

■4K x 9 organization (CY7C139)

■0.65-micron CMOS for optimum speed and power

■High speed access: 15 ns

■Low operating power: ICC = 160 mA (max.)

■Fully asynchronous operation

■Automatic power down

■TTL compatible

■Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device

■On-chip arbitration logic

■Semaphores included to permit software handshaking between ports

■INT flag for port-to-port communication

■Available in 68-pin PLCC

■Pb-free packages available

Functional Description

The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C138/9 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138/9 can be used as a standalone 8/9-bit dual-port static RAM or multiple devices can be combined to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multipro- cessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin.

The CY7C138 and CY7C139 are available in a 68-pin PLCC.

Logic Block Diagram

Notes

 

 

 

 

1.

BUSY

is an output in master mode and an input in slave mode.

 

 

 

 

2.

Interrupt: push-pull output and requires no pull-up resistor.

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-06037 Rev. *D

 

Revised March 12, 2009

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Cypress CY7C139, CY7C138 manual Features, Functional Description, Logic Block Diagram
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CY7C138, CY7C139 specifications

The Cypress CY7C139 and CY7C138 are advanced static random-access memory (SRAM) components that have garnered attention in the field of digital electronics due to their high performance and reliability. These SRAMs are designed to meet the demanding needs of a variety of applications, ranging from telecommunications to automotive systems and consumer electronics.

The CY7C139 is a 128K x 8 bit static RAM, while the CY7C138 is a 256K x 8 bit SRAM, offering flexible memory solutions for designers. Both devices utilize a fast access time, typically around 10 to 15 nanoseconds, allowing quick data retrieval essential for high-speed applications. This remarkable speed is complemented by low power consumption, making them suitable for battery-operated devices and other applications where efficiency is paramount.

One of the key features of the CY7C139 and CY7C138 is their asynchronous operation, which enables them to provide high-speed data access without the need for a clock signal. This characteristic simplifies system design and enhances performance, as users can write to and read from the memory without waiting for synchronization. The devices support standard CMOS interface levels, which facilitate integration into a diverse range of digital systems.

Additionally, these SRAMs have been designed with a low standby current, making them particularly effective for low-power applications. The devices also include a robust input/output structure that ensures reliable signal integrity under various operating conditions. Their built-in data retention capability allows the SRAMs to retain stored data even during power failures, a critical feature in many systems that require data preservation.

Both CY7C139 and CY7C138 SRAMs support a wide range of temperature and voltage ranges, making them suitable for industrial and automotive environments. They are packaged in industry-standard configurations, allowing for easy integration into existing designs.

In summary, the Cypress CY7C139 and CY7C138 SRAMs provide high-speed, low-power memory solutions suitable for various applications. Their asynchronous operation, low standby current, and robust performance characteristics make them a preferred choice for engineers looking to enhance system efficiency and reliability. These features make the CY7C139 and CY7C138 indispensable components in modern digital electronic designs.
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