CY7C138, CY7C139
Document #: 38-06037 Rev. *D Page 8 of 17
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[22, 24, 25]
Figure 8. Semaphore Read After Write Timing, Either Side[26]
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE tLZOE
SEMOR CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
SEMOR CE
R/W
DATAOUT
DATA IN
tLZWE
DATAVALID
ADDRESS
Notes
20.BUSY = HIGH for the writing port.
21.CEL = CER = LOW.
22.The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
23.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not
apply and the write pulse can be as short as the specified tPWE.
24.R/W must be HIGH during all address transitions.
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