CY7C138, CY7C139
Document #: 38-06037 Rev. *D Page 6 of 17
tHD Data Hold From Write End 0 0 0 0 ns
tHZWE[11,12] R/W LOW to High Z 10 15 20 25 ns
tLZWE[11,12] R/W HIGH to Low Z 3 3 3 3 ns
tWDD[13] Write Pulse to Data Delay 30 50 60 70 ns
tDDD[13] Write Data Valid to Read Data Valid 25 30 35 40 ns
BUSY TIMING[14]
tBLA BUSY LOW from Address Match 15 20 20 45 ns
tBHA BUSY HIGH from Address Mismatch 15 20 20 40 ns
tBLC BUSY LOW from CE LOW 15 20 20 40 ns
tBHC BUSY HIGH from CE HIGH 15 20 20 35 ns
tPS Port Set-Up for Priority 5 5 5 5 ns
tWB R/W LOW after BUSY LOW 0 0 0 0 ns
tWH R/W HIGH after BUSY HIGH 13 20 30 40 ns
tBDD[15] BUSY HIGH to Data Valid Note 15 Note 15 Note 15 Note 15 ns
INTERRUPT TIMING[14]
tINS INT Set Time 15 25 25 30 ns
tINR INT Reset Time 15 25 25 30 ns
SEMAPHORE TIMING
tSOP SEM Flag Update Pulse (OE or SEM)10 10 15 20 ns
tSWRD SEM Flag Write to Read Time 5 5 5 5 ns
tSPS SEM Flag Contention Window 5 5 5 5 ns
Switching Characteristics Over the Operating Range[9] (continued)
Parameter Description
7C138-15
7C139-15
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55 Unit
Min Max Min Max Min Max Min Max
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
10.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
11.Test conditions used are Load 3.
12.This parameter is guaranteed but not tested.
13.For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14.Test conditions used are Load 2.
15.tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
Figure 3. Read Cycle No. 1 (Either Port Address Access)[16, 17]
Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)[16, 18, 19]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
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