Cypress CY7C138, CY7C139 manual Switching Waveforms, Timing, Busy, Data OUT, Previous Data Valid

CY7C138, CY7C139

Switching Characteristics Over the Operating Range[9] (continued)

																7C138-15		7C138-25		7C138-35		7C138-55
Parameter							Description									7C139-15		7C139-25		7C139-35		7C139-55		Unit
																Min	Max	Min	Max	Min	Max	Min	Max
tHD		Data Hold From Write End														0		0		0		0		ns
tHZWE[11,12]
		R/W			LOW to High Z												10		15		20		25	ns
tLZWE[11,12]
		R/W			HIGH to Low Z											3		3		3		3		ns
tWDD[13]		Write Pulse to Data Delay															30		50		60		70	ns
tDDD[13]		Write Data Valid to Read Data Valid															25		30		35		40	ns
BUSY TIMING	[14]
tBLA		BUSY					LOW from Address Match										15		20		20		45	ns
tBHA							HIGH from Address Mismatch										15		20		20		40	ns
		BUSY
tBLC							LOW from					LOW					15		20		20		40	ns
		BUSY							CE
tBHC							HIGH from					HIGH					15		20		20		35	ns
		BUSY								CE
tPS		Port Set-Up for Priority														5		5		5		5		ns
tWB
		R/W		LOW after BUSY LOW												0		0		0		0		ns
tWH					HIGH after						HIGH					13		20		30		40		ns
		R/W						BUSY
tBDD[15]						HIGH to Data Valid											Note 15		Note 15		Note 15		Note 15	ns
		BUSY
INTERRUPT	TIMING[14]
tINS		INT	Set Time														15		25		25		30	ns
tINR			Reset Time														15		25		25		30	ns
		INT
SEMAPHORE TIMING
tSOP		SEM Flag Update Pulse											(OE	or	SEM)	10		10		15		20		ns
tSWRD		SEM Flag Write to Read Time														5		5		5		5		ns
tSPS		SEM Flag Contention Window														5		5		5		5		ns

Switching Waveforms

Figure 3. Read Cycle No. 1 (Either Port Address Access)[16, 17]

ADDRESS				tRC
			tAA
DATA OUT		tOHA
	PREVIOUS DATA VALID				DATA VALID

Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)[16, 18, 19]

Notes

9.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance.

10.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

11.Test conditions used are Load 3.

12.This parameter is guaranteed but not tested.

13.For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.

14.Test conditions used are Load 2.

15.tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).

Document #: 38-06037 Rev. *D Page 6 of 17

[+] Feedback