Data OUT Data Valid, Address R Match | Cypress CY7C139, CY7C138

		CY7C138, CY7C139
Switching Waveforms (continued)
SEM or CE
tACE		tHZCE
OE
	tDOE	tHZOE
tLZOE	tDOE
tLZCE
DATA OUT	DATA VALID
tPU		t
ICC		PD
ICC
ISB
Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[20, 21]
	tWC
ADDRESS R	MATCH
R/WR	tPWE
	tSD	tHD
DATA INR	VALID
ADDRESS L	MATCH
		tDDD
DATAOUTL		VALID
	tWDD

Notes

16.R/W is HIGH for read cycle.

17.Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.

18.Address valid prior to or coincident with CE transition LOW.

19.CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.

Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24]

Document #: 38-06037 Rev. *D

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Cypress CY7C139, CY7C138 manual Data OUT Data Valid, Address R Match, Data INR Valid Address L Match, Data Outl Valid

CY7C138, CY7C139 specifications

The Cypress CY7C139 and CY7C138 are advanced static random-access memory (SRAM) components that have garnered attention in the field of digital electronics due to their high performance and reliability. These SRAMs are designed to meet the demanding needs of a variety of applications, ranging from telecommunications to automotive systems and consumer electronics.

The CY7C139 is a 128K x 8 bit static RAM, while the CY7C138 is a 256K x 8 bit SRAM, offering flexible memory solutions for designers. Both devices utilize a fast access time, typically around 10 to 15 nanoseconds, allowing quick data retrieval essential for high-speed applications. This remarkable speed is complemented by low power consumption, making them suitable for battery-operated devices and other applications where efficiency is paramount.

One of the key features of the CY7C139 and CY7C138 is their asynchronous operation, which enables them to provide high-speed data access without the need for a clock signal. This characteristic simplifies system design and enhances performance, as users can write to and read from the memory without waiting for synchronization. The devices support standard CMOS interface levels, which facilitate integration into a diverse range of digital systems.

Additionally, these SRAMs have been designed with a low standby current, making them particularly effective for low-power applications. The devices also include a robust input/output structure that ensures reliable signal integrity under various operating conditions. Their built-in data retention capability allows the SRAMs to retain stored data even during power failures, a critical feature in many systems that require data preservation.

Both CY7C139 and CY7C138 SRAMs support a wide range of temperature and voltage ranges, making them suitable for industrial and automotive environments. They are packaged in industry-standard configurations, allowing for easy integration into existing designs.

In summary, the Cypress CY7C139 and CY7C138 SRAMs provide high-speed, low-power memory solutions suitable for various applications. Their asynchronous operation, low standby current, and robust performance characteristics make them a preferred choice for engineers looking to enhance system efficiency and reliability. These features make the CY7C139 and CY7C138 indispensable components in modern digital electronic designs.

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional Description Unit Pin ConfigurationsPin Definitions Left Port Right Port Description Selection Guide Description Operating Range Electrical Characteristics Over the Operating RangeTemperature Maximum Ratings Parameter Description Test Conditions Max Unit Capacitance8 ALL Input Pulses Switching Characteristics Over the Operating Range9Output GND Data OUT Switching WaveformsTiming Busy Data Outl Valid Data OUT Data ValidAddress R Match Data INR Valid Address L Match Address Address SEM or CEData Data Valid High Impedance Write Cycle Read Cycle Valid AddressSEM Dataout Valid Busyl Addressr MatchData INR Valid Addressl Match Address Match Address Mismatch Address L,R Address Match CEL CER BusyrADDRESSL,R CER CEL Busy L Address L Addressr Busyr Right Side Sets Intl Right Side Clears INT RLeft Side Clears Intl Write Operation Architecture Interrupt Operation Example assumes Non-Contending Read/Write Inputs Outputs OperationRight Port Function Normalized Supply Voltage Ambient Temperature C Output VoltageNormalized Supply Current Output Source Current Package Type Operating Package DiagramOrdering Information Speed Ordering Code Document History Sales, Solutions and Legal Information

Cypress CY7C139, CY7C138 Data OUT Data Valid, Address R Match, Data INR Valid Address L Match

Models: CY7C138 CY7C139

CY7C138, CY7C139

Switching Waveforms (continued)

DATA OUT

DATA VALID

Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[20, 21]

ADDRESS R

MATCH

DATA INR

VALID

ADDRESS L

MATCH

DATAOUTL

VALID

Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24]

CY7C138, CY7C139 specifications