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Cypress CY7C139 manual Valid Address, Dataout Valid, Write Cycle Read Cycle, Seml Match, Semr

Models: CY7C138 CY7C139

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			CY7C138, CY7C139
Switching Waveforms (continued)
		tAA	tOHA
A0–A 2	VALID ADDRESS	VALID ADDRESS
	tAW	tACE
	tHA	tACE
SEM	tHA
SEM	tSCE	tSOP
	tSCE	tSOP
	tSD
I/O0	DATAIN VALID		DATAOUT VALID
	DATAIN VALID		DATAOUT VALID
tSA	tHD
tSA	tPWE
R/W
	tSWRD	tDOE
OE		tSOP
	WRITE CYCLE	READ CYCLE

Figure 9. Timing Diagram of Semaphore Contention[27, 28, 29]

A0L–A2L

R/WL

SEML

MATCH

tSPS

A0R–A2R

MATCH

R/WR

SEMR

Notes

25.Data I/O pins enter high impedance when OE is held LOW during write.

26.CE = HIGH for the duration of the above timing (both write and read cycle).

Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)[21]

Document #: 38-06037 Rev. *D

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Cypress CY7C139, CY7C138 manual Valid Address, Dataout Valid, Write Cycle Read Cycle, Seml Match, Semr

CY7C138, CY7C139 specifications

The Cypress CY7C139 and CY7C138 are advanced static random-access memory (SRAM) components that have garnered attention in the field of digital electronics due to their high performance and reliability. These SRAMs are designed to meet the demanding needs of a variety of applications, ranging from telecommunications to automotive systems and consumer electronics.

The CY7C139 is a 128K x 8 bit static RAM, while the CY7C138 is a 256K x 8 bit SRAM, offering flexible memory solutions for designers. Both devices utilize a fast access time, typically around 10 to 15 nanoseconds, allowing quick data retrieval essential for high-speed applications. This remarkable speed is complemented by low power consumption, making them suitable for battery-operated devices and other applications where efficiency is paramount.

One of the key features of the CY7C139 and CY7C138 is their asynchronous operation, which enables them to provide high-speed data access without the need for a clock signal. This characteristic simplifies system design and enhances performance, as users can write to and read from the memory without waiting for synchronization. The devices support standard CMOS interface levels, which facilitate integration into a diverse range of digital systems.

Additionally, these SRAMs have been designed with a low standby current, making them particularly effective for low-power applications. The devices also include a robust input/output structure that ensures reliable signal integrity under various operating conditions. Their built-in data retention capability allows the SRAMs to retain stored data even during power failures, a critical feature in many systems that require data preservation.

Both CY7C139 and CY7C138 SRAMs support a wide range of temperature and voltage ranges, making them suitable for industrial and automotive environments. They are packaged in industry-standard configurations, allowing for easy integration into existing designs.

In summary, the Cypress CY7C139 and CY7C138 SRAMs provide high-speed, low-power memory solutions suitable for various applications. Their asynchronous operation, low standby current, and robust performance characteristics make them a preferred choice for engineers looking to enhance system efficiency and reliability. These features make the CY7C139 and CY7C138 indispensable components in modern digital electronic designs.

Contents

Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPin Definitions Left Port Right Port Description Pin ConfigurationsSelection Guide Description UnitTemperature Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit Capacitance8Output Switching Characteristics Over the Operating Range9GND ALL Input PulsesTiming Switching WaveformsBusy Data OUTAddress R Match Data OUT Data ValidData INR Valid Address L Match Data Outl ValidData Data Valid Address SEM or CEHigh Impedance AddressSEM Valid AddressDataout Valid Write Cycle Read CycleData INR Valid Addressr MatchAddressl Match BusylADDRESSL,R CER CEL Busy L Address L,R Address Match CEL CER BusyrAddress L Addressr Busyr Address Match Address MismatchRight Side Clears INT R Right Side Sets IntlLeft Side Clears Intl Write Operation ArchitectureNon-Contending Read/Write Inputs Outputs Operation Interrupt Operation Example assumesRight Port Function Normalized Supply Current Supply Voltage Ambient Temperature C Output VoltageOutput Source Current NormalizedOrdering Information Package DiagramSpeed Ordering Code Package Type OperatingDocument History Sales, Solutions and Legal Information

CY7C138, CY7C139

Switching Waveforms (continued)

VALID ADDRESS

SEM

DATAOUT VALID

WRITE CYCLE

READ CYCLE

Figure 9. Timing Diagram of Semaphore Contention[27, 28, 29]

SEML

MATCH

SEMR

Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)[21]

CY7C138, CY7C139 specifications