Cypress CY7C138, CY7C139 Ordering Information, Package Diagram

CY7C138, CY7C139

Document #: 38-06037 Rev. *D Page 16 of 17

Ordering Information

4K x8 Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

15 CY7C138-15JC J81 68-Lead Plastic Leaded Chip Carrier Commercial

CY7C138-15JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier

25 CY7C138-25JC J81 68-Lead Plastic Leaded Chip Carrier Commercial

CY7C138-25JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier

CY7C138-25JI J81 68-Lead Plastic Leaded Chip Carrier Industrial

CY7C138-25JXI J81 68-Lead Pb-Free Plastic Leaded Chip Carrier

35 CY7C138-35JC J81 68-Lead Plastic Leaded Chip Carrier Commercial

CY7C138-35JI J81 68-Lead Plastic Leaded Chip Carrier Industrial

55 CY7C138-55JC J81 68-Lead Plastic Leaded Chip Carrier Commercial

CY7C138-55JI J81 68-Lead Plastic Leaded Chip Carrier Industrial

Package Diagram

Figure 16. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005)

51-85005-*A

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Contents

Main CY7C138, CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description Logic Block Diagram Pin Configurations Figure 1. 68-Pin PLCC (Top View) Table 2. Selection Guide Description 7C138-15 7C139-15 7C138-25 7C139-25 7C138-35 7C139-35 CY7C138, CY7C139 Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics Switching Waveforms CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 7 of 17 Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[20, 21] Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24] CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 8 of 17 Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[22, 24, 25] Figure 8. Semaphore Read After Write Timing, Either Side CY7C138, CY7C139 Figure 9. Timing Diagram of Semaphore Contention[27, 28, 29] Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)[21] Figure 11. Write Timing with Busy Input (M/S=LOW) Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)[30] Figure 13. Busy Timing Diagram No. 2 (Address Arbitration) CEL Valid Firs t: CER Valid First: Left Address Valid First: Right Address Valid First: Figure 14. Interrupt Timing Diagrams Left Side Sets INTR: Left Side Clears INTL: Right Side Clears INTR: Right Side Sets INTL: CY7C138, CY7C139 Architecture Functional Description Write Operation Read Operation Page Figure 15. Typical DC and AC Characteristics Ordering Information 4K x8 Dual-Port SRAM Package Diagram Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions