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Cypress CY7C1381D, CY7C1383F, CY7C1381F, CY7C1383D manual Timing Diagrams, Read Cycle Timing

Models: CY7C1381D CY7C1381F CY7C1383D CY7C1383F

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CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Timing Diagrams

Read Cycle Timing [26]

tCYC

CLK

t CH

tADS tADH

t CL

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS

GW, BWE,BW

A1	A2
t WES	t WEH
tCES t CEH	Deselect Cycle
tCES t CEH
	t ADVS t ADVH

ADV
OE
		tOEV
		tOEHZ
		tCLZ
Data Out (Q)	High-Z	Q(A1)

tCDV

Single READ

ADV suspends burst

t	tCDV
	OELZ
	tCHZ
	tDOH

Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A2 + 2)
				Burst wraps around
		BURST		to its initial state
		BURST
		READ
	DON’T CARE	UNDEFINED

Note:

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05544 Rev. *F

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Cypress CY7C1381D, CY7C1383F, CY7C1381F, CY7C1383D manual Timing Diagrams, Read Cycle Timing

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.

Contents

Selection Guide Features133 MHz 100 MHz Unit Cypress Semiconductor Corporation CY7C1381D, CY7C1381F Pin Configurations Pin Tqfp Pinout 3 Chip Enable CY7C1381D 512K xCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Pin Definitions Name DescriptionByte write select inputs, active LOW. Qualified with Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress = GND CE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description Used Function CY7C1381D/CY7C1381F Truth Table for Read/Write 4DQPB, Dqpa DQPC, Dqpa TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass Register TAP Timing TAP AC Switching Characteristics 3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions Min Scan Register Sizes Identification Register DefinitionsIdentification Codes Bit Size ×36 Bit Size ×18 Bit # Ball ID Ball BGA Boundary Scan Order 14 A11 Maximum Ratings Electrical CharacteristicsOperating Range Ambient Range Capacitance Thermal ResistanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching Characteristics Read Cycle Timing Timing Diagrams Address BWE Write Cycle Timing 26 ADV Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change