Cypress CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F Write Cycle Timing

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 22 of 29

Write Cycle Timing [26, 27]

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1) D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for ﬁrst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

BW X

ADV

Data in (D)

Data Out (Q)

Note:

27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

[+] Feedback

Contents

Main 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Features Functional Description Selection Guide Logic Block Diagram CY7C1381D/CY7C1381F [3] (512K x 36) Logic Block Diagram CY7C1383D/CY7C1383F[3] (1M x 18) DQs DQP DQP Note: 3. CY7C1381F and CY7C1383F have only 1 chip enable (CE1). CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 3 of 29 Pin Configurations CY7C1381D (512K x 36) CY7C1383D (1M x 18) Pin Configurations CY7C1381F (512K x 36) CY7C1383F (1M x 18) 119-Ball BGA Pinout Pin Configurations 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381D (512K x 36) CY7C1383D (1M x 18) 2345671 A B C D E F G H J K L M N P R 891011 Pin Definitions CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Functional Overview Pin Definitions CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F TAP Ti min g TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order[14, 16] Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Timing Diagrams Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing ZZ Mode Timing Ordering Information Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 3. 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180) SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Package Diagrams NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D - NOTES : PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC Document History Page