CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Pin Definitions

 

 

 

 

 

 

 

Name

IO

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

A0, A1, A

Input-

Address inputs used to select one of the address locations. Sampled at the rising edge

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

of the CLK if ADSP or

ADSC

is active LOW, and CE

1

, CE , and CE

[2] are sampled active.

 

 

 

 

 

 

 

 

 

 

 

 

 

A[1:0] feed the 2-bit counter.

2

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,

 

 

 

B

Input-

Byte write select inputs, active LOW. Qualified with

 

to conduct byte writes to the

 

BW

BW

BWE

 

BWC, BWD

Synchronous

SRAM. Sampled on the rising edge of CLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

global write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).

 

CLK

Input-

Clock input. Used to capture all synchronous inputs to the device. Also used to increment

 

 

 

 

 

 

 

 

 

 

 

 

Clock

the burst counter when ADV is asserted LOW, during a burst operation.

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

Input-

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

with CE2 and

CE

3 [2] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

is sampled only when a new external address is loaded.

 

 

 

 

 

 

 

 

CE2

Input-

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled only when a new

 

 

 

 

 

 

 

 

 

 

 

 

 

external address is loaded.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 [2]

Input-

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external

 

 

 

 

 

 

 

 

 

 

 

 

 

address is loaded.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,

 

 

 

 

 

 

 

 

 

 

 

 

 

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

 

 

 

 

 

 

 

 

 

 

 

 

 

from a deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

increments the address in a burst cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from processor, sampled on the rising edge of CLK, active LOW.

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

 

 

 

 

 

 

 

 

 

 

 

 

 

registers. A[1:0] are also loaded into

the burst counter. When ADSP and

ADSC

are both

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted, only ADSP is recognized.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ASDP is ignored when CE1 is deasserted HIGH.

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from controller, sampled on the rising edge of CLK, active LOW.

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

 

 

 

 

 

 

 

 

 

 

 

 

 

registers. A[1:0] are also loaded into the burst counter. When ADSP and

ADSC

are both

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted, only ADSP is recognized.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

must be asserted LOW to conduct a byte write.

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

Input-

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

condition with data integrity preserved. For normal operation, this pin has to be LOW or left

 

 

 

 

 

 

 

 

 

 

 

 

 

floating. ZZ pin has an internal pull down.

 

 

 

 

 

 

 

 

 

 

 

 

DQs

IO-

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

 

 

 

 

 

 

 

 

 

 

 

 

 

memory location specified by the addresses presented during the previous clock rise of the

 

 

 

 

 

 

 

 

 

 

 

 

 

read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the

 

 

 

 

 

 

 

 

 

 

 

 

 

pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The

 

 

 

 

 

 

 

 

 

 

 

 

 

outputs are automatically tri-stated during the data portion of a write sequence, during the

 

 

 

 

 

 

 

 

 

 

 

 

 

first clock when emerging from a deselected state, and when the device is deselected,

 

 

 

 

 

 

 

 

 

 

 

 

 

regardless of the state of OE.

 

 

 

 

 

 

 

 

 

 

 

 

DQPX

IO-

Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

write sequences, DQPX is controlled by BWX correspondingly.

 

 

 

Document #: 38-05544 Rev. *F

 

 

 

 

 

 

 

 

 

 

 

 

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Cypress CY7C1381F, CY7C1383F manual Pin Definitions, Name Description, Byte write select inputs, active LOW. Qualified with

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.