Cypress CY7C1460AV33, CY7C1464AV33 manual Logic Block Diagram-CY7C1462AV33 2M x, Selection Guide

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Logic Block Diagram-CY7C1462AV33 (2M x 18)
	A0, A1, A	ADDRESS
		REGISTER 0		A1	D1	Q1 A1'
	MODE			A0	D0 BURST Q0 A0'
				ADV/LD		LOGIC
CLK	C
				C
CEN
		WRITE ADDRESS		WRITE ADDRESS
		REGISTER 1		REGISTER 2
									O		O
									U		U
								S	T	D	T
									P		P
	ADV/LD							E	U	A	U
				WRITE REGISTRY				N	T	T	T
							MEMORY	S	R	A	B
	BWa			AND DATA COHERENCY		WRITE		E
							ARRAY		E	S	U
				CONTROL LOGIC		DRIVERS		A	G
										T	F
	BWb							M	I	E	F
								P	S	E	E
								S	T	R	R
									E	I	S
	WE								R	N
									S
										G
									E		E
							INPUT	E		INPUT	E
							REGISTER 1			REGISTER 0
	OE		READ LOGIC
	CE1
	CE2
	CE3
	ZZ		Sleep
			Control

DQs DQPa DQPb

Logic Block Diagram-CY7C1464AV33 (512K x 72)

	A0, A1, A	ADDRESS
		REGISTER 0		A1	D1	Q1 A1'
	MODE			A0	D0 BURST Q0 A0'
				ADV/LD		LOGIC
CLK	C
				C
CEN
		WRITE ADDRESS		WRITE ADDRESS
		REGISTER 1		REGISTER 2
									O		O
									U		U
									T		T
	ADV/LD							S	P	D	P
								E	U	A	U
	BWa			WRITE REGISTRY				N	T	T	T
							MEMORY	S	R	A
	BWb			AND DATA COHERENCY		WRITE		E		S	B
				CONTROL LOGIC			ARRAY	A	E		U
	BWc					DRIVERS			G	T	F
	BWd							M	I	E	F
								P	S	E	E
	BWe							S	T	R	R
									E
	BWf									I	S
									R	N
	BWg								S	G
									E		E
	BWh
	WE
							INPUT	E		INPUT	E
							REGISTER 1			REGISTER 0
	OE		READ LOGIC
	CE1
	CE2
	CE3
	ZZ		Sleep
			Control

DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh

Selection Guide

	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	2.6	3.2	3.4	ns
Maximum Operating Current	475	425	375	mA
Maximum CMOS Standby	120	120	120	mA
Current

Document #: 38-05353 Rev. *D Page 2 of 27

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