Clock input to the Jtag circuitry | Cypress CY7C1462AV33, CY7C1464AV33

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

Clock

CEN. CLK is only recognized if CEN is active LOW.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous

with CE2 and CE3 to select/deselect the device.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

Synchronous

conjunction with CE1 and CE3 to select/deselect the device.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous

with CE1 and CE2 to select/deselect the device.

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device

Asynchronous

to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as

outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is

masked during the data portion of a write sequence, during the first clock when emerging

from a deselected state and when the device has been deselected.

Input-

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by

CEN

Synchronous

the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN

does not deselect the device,

CEN

can be used to extend the previous cycle when required.

DQa

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

DQb

Synchronous

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

DQc

memory location specified by AX during the previous clock rise of the read

cycle. The

DQd

direction of the pins is controlled by OE and the internal control logic. When OE is asserted

DQe

LOW, the pins can behave as outputs. When HIGH, DQa–DQdare placed in a tri-state

DQf

condition. The outputs are automatically tri-stated during the data portion of a write

DQg

sequence, during the first clock when emerging

from a deselected state, and when the

DQh

device is deselected, regardless of the state of OE.

DQPa,DQPb,

I/O-

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].

DQPc,DQPd

Synchronous

During write sequences, DQPa is controlled by

a, DQPb is controlled by BWb, DQPc is

DQPe,DQPf

controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is

DQPg,DQPh

controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst

order. Pulled LOW selects the linear burst order. MODE should not change states during

operation. When left floating MODE will default HIGH, to an interleaved burst order.

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

TDI

JTAG serial input

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

TMS

Test Mode Select

This pin controls the Test Access Port state machine. Sampled on the rising edge of

Synchronous

TCK.

TCK

JTAG-Clock

Clock input to the JTAG circuitry.

VDD

Power Supply

Power supply inputs to the core of the device.

VDDQ

I/O Power Supply

Power supply for the I/O circuitry.

VSS

Ground

Ground for the device. Should be connected to ground of the system.

N/A

No connects. This pin is not connected to the die.

NC/72M

N/A