CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 6 of 27
CLK Input-
Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE Input-
Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.
CEN Input-
Synchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
I/O-
Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by AX during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state
condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPa,DQPb,
DQPc,DQPd
DQPe,DQPf
DQPg,DQPh
I/O-
Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].
During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is
controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is
controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
TDO JTAG serial output
Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI JTAG serial input
Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
TMS Test Mode Select
Synchronous This pin controls the Test Access Port state machine. Sampled on the rising edge of
TCK.
TCK JTAG-Clock Clock input to the JTAG circuitry.
VDD Power Supply Power supply inputs to the core of the device.
VDDQ I/O Power Supply Power supply for the I/O circuitry.
VSS Ground Ground for the device. Should be connected to ground of the system.
NC N/A No connects. This pin is not connected to the die.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
NC/576M N/A Not connected to the die. Can be tied to any voltage level.
NC/1G N/A Not connected to the die. Can be tied to any voltage level.
ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected
to VSS or left floating. ZZ pin has an internal pull-down.
Pin Definitions (continued)
Pin Name I/O Type Pin Description
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