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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
When the TAP controller is in the
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The length of the Boundary Scan Register for the SRAM in different packages is listed in the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the
The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instruc- tions are described in detail below.
Instructions are loaded into the TAP controller during the
IDCODE
The IDCODE instruction causes a
The IDCODE instruction is loaded into the instruction register upon
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the
The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the
To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture
Once the data is captured, it is possible to shift out the data by putting the TAP into the
PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a
EXTEST
The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a
The boundary scan register has a special bit located at bit #89 (for
Document #: | Page 11 of 27 |
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