CY7C1460AV33
CY7C1462AV33
CY7C1464AV33

Document #: 38-05353 Rev. *D Page 5 of 27

Pin Definitions

Pin Name I/O Type Pin Description

A0

A1

A

Input-

Synchronous Address Inputs used to select one of the address locations. Sampled at the rising

edge of the CLK.

BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh

Input-

Synchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and

DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and

DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and

DQPh.

WE Input-

Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active

LOW. This signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous Advance/Load Input used to advance the on-chip address counter or load a new

address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.

When LOW, a new address can be loaded into the device for an access. After being

deselected, ADV/LD should be driven LOW in order to load a new address.

Pin Configurations (continued)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

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DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
AA AA
NC NC
NC/144M NC/72M A NC/288M
AAA
AAAA1
A0
AAA
AA
A
NC/576M
NC
NC
NC NC
NC
BWSbBWSf
BWSeBWSa
BWScBWSg
BWSd
BWSh
TMS TDI TDO TCK
NC
NC MODE NC
CEN VSS
NC
CLK NC VSS
VDD VDD VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS VSS
VSS
VSS
VSS
VSS VSS
VSS
NC/1G
VDD
NC
OE
CE3
CE1
CE2ADV/LD
WE
VSS
VSS
VSS
VSS VSS VSS VSS
ZZ
VSS VSS VSS VSS
NC
VDDQ
VSS
VSS NC VSS VSS
VSS VSS VSS VSS
NC
VSS
VDDQ VDDQ VDDQ VDDQ
VDDQ NC VDDQ VDDQ
VDDQ VDDQ NC VDDQ VDDQ
VDDQ VDDQ NC VDDQ VDDQ
VDDQ
VDDQ
VDDQ VDDQ
VDDQ VDDQ VDDQ VDDQ
209-ball FBGA (14 x 22 x 1.76 mm) PinoutCY7C1464AV33 (512K x 72)
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