Cypress CY7C1470BV33, CY7C1472BV33, CY7C1474BV33 CY7C1470BV33 CY7C1472BV33, CY7C1474BV33

CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Document #: 001-15031 Rev. *C Page 3 of 30
Logic Block Diagram – CY7C1474BV33 (1M x 72)
A0,A1, A
C
MODE
CE1
CE2
CE3
OE
READLOGIC
DQs
DQP
a
DQP b
DQP
c
DQP d
DQP e
DQP
f
DQP
g
DQP h
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER0
ADDRESS
REGISTER0
WRITEADDRESS
REGISTER1
WRITEADDRESS
REGISTER2
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
BW
a
BW b
WE
ZZ
Sleep
Control
BW c
WRITEREGISTRY
ANDDATA COHERENCY
CONTROLLOGIC
BW d
BW e
BW f
BW
g
BW h
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