Cypress CY7C1470BV33, CY7C1472BV33, CY7C1474BV33 Ordering Information

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 26 of 30

250 CY7C1470BV33-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial

CY7C1472BV33-250AXC

CY7C1470BV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1472BV33-250BZC

CY7C1470BV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free

CY7C1472BV33-250BZXC

CY7C1474BV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474BV33-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

CY7C1470BV33-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Industrial

CY7C1472BV33-250AXI

CY7C1470BV33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1472BV33-250BZI

CY7C1470BV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free

CY7C1472BV33-250BZXI

CY7C1474BV33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474BV33-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Part and Package Type Operating

Range

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Contents

Main 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Features Functional Description Selection Guide CY7C1472BV33, CY7C1474BV33 Logic Block Diagram CY7C1470BV33 (2M x 36) C ADV/LD P CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 3 of 30 Logic Block Diagram CY7C1474BV33 (1M x 72) ZZ ADV/LD CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Pin Configurations (2M x 36) (4M x 18) MODE CY7C1472BV33 Pin Configurations 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV33 (2M x 36) CY7C1472BV33 (4M x 18) 2345671 A B C D E F G H J K L M N P R 891011 Pin Configurations CY7C1474BV33 (1M 72) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout A B C D E F G H J K L M N P R T U V W 1234 567 89 1110 CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Functional Overview Single Read Accesses Burst Read Accesses Single Write Accesses Burst Write Accesses ZZ Mode Electrical Characteristics Page Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port (TAP) Performing a TAP Reset TAP Registers TAP Instruction Set CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions 50 TDO 50 Page Page Boundary Scan Exit Order (1M x 72) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Electrical Characteristics Switching Characteristics Switching Waveforms Figure 5 shows read-write timing waveform.[20, 21, 22] Figure 5. Read/Write Timing OE n-Out (DQ) BW Switching Waveforms I CLK ZZ LL INPUTS (except ZZ) Outputs (Q) Page Ordering Information Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams 51-85165-*A Page Document History Page