Cypress CY7C1470BV33, CY7C1472BV33, CY7C1474BV33 Maximum Ratings , Operating Range , Electrical Characteristics

CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Document #: 001-15031 Rev. *C Page 20 of 30
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC to Outputs in Tri-State....................–0.5V to VDDQ + 0.5V
DC Input Voltage................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range Ambient
Temper ature VDD VDDQ
Commercial 0°C to +70°C 3.3V
–5%/+10% 2.5V – 5% to VDD
Industrial –40°C to +85°C
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter Description Test Conditions Min Max Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ IO Supply Voltage For 3.3V IO 3.135 VDD V
For 2.5V IO 2.375 2.625 V
VOH Output HIGH Voltage For 3.3V IO, IOH = −4.0 mA 2.4 V
For 2.5V IO, IOH= −1.0 mA 2.0 V
VOL Output LOW Voltage For 3.3V IO, IOL= 8.0 mA 0.4 V
For 2.5V IO, IOL= 1.0 mA 0.4 V
VIH Input HIGH Voltage[13] For 3.3V IO 2.0 VDD + 0.3V V
For 2.5V IO 1.7 VDD + 0.3V V
VIL Input LOW Voltage[13] For 3.3V IO –0.3 0.8 V
For 2.5V IO –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5μA
Input Current of MODE Input = VSS –30 μA
Input = VDD 5μA
Input Current of ZZ Input = VSS –5 μA
Input = VDD 30 μA
IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5μA
IDD [15] VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 500 mA
5.0-ns cycle, 200 MHz 500 mA
6.0-ns cycle, 167 MHz 450 mA
ISB1 Automatic CE
Power Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 245 mA
5.0-ns cycle, 200 MHz 245 mA
6.0-ns cycle, 167 MHz 245 mA
ISB2 Automatic CE
Power Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
f = 0
All speed grades 120 mA
Notes
13.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC)> –2V (pulse width less than tCYC/2).
14.TPower-up: assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
15.The operation current is calculated with 50% read cycle and 50% write cycle.
[+] Feedback