Cypress CY7C1472BV33, CY7C1474BV33, CY7C1470BV33 manual Functional Description, Selection Guide

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Features

■Pin-compatible and functionally equivalent to ZBT™

■Supports 250 MHz bus operations with zero wait states

❐Available speed grades are 250, 200, and 167 MHz

■Internally self-timed output buffer control to eliminate the need to use asynchronous OE

■Fully registered (inputs and outputs) for pipelined operation

■Byte Write capability

■Single 3.3V power supply

■3.3V/2.5V IO power supply

■Fast clock-to-output time

❐3.0 ns (for 250-MHz device)

■Clock Enable (CEN) pin to suspend operation

■Synchronous self-timed writes

■CY7C1470BV33, CY7C1472BV33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV33 available in Pb-free and non-Pb-free 209-ball FBGA package

■IEEE 1149.1 JTAG Boundary Scan compatible

■Burst capability—linear or interleaved burst order

■“ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BWa–BWdfor CY7C1470BV33, BWa–BWbfor CY7C1472BV33, and BWa–BWhfor CY7C1474BV33) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Selection Guide

Description	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	3.0	3.0	3.4	ns
Maximum Operating Current	500	500	450	mA
Maximum CMOS Standby Current	120	120	120	mA

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-15031 Rev. *C		Revised February 29, 2008

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