Cypress CY7C1511V18, CY7C1513V18, CY7C1515V18, CY7C1526V18 Switching Characteristics

CY7C1511V18, CY7C1526V18
CY7C1513V18, CY7C1515V18
Document Number: 38-05363 Rev. *F Page 25 of 32
Output Times
tCO tCHQV C/C Clock Rise (or K/K in single
clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data Output Hold after Output C/C
Clock Rise (Active to Active) –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock
Rise –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data Valid 0.27 0.27 0.30 0.35 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z
(Active to High-Z) [26, 27] – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [26, 27] –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycles
tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns
Switching Characteristics (continued)
Over the Operating Range [22, 23]
Cypress
Parameter Consortium Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit
Min Max Min Max Min Max Min Max Min Max
Notes
26.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms on page 23. Transition is measured ± 100 mV from steady-state voltage.
27.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
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