CY8C24223A, CY8C24423A
Table 6. Register Map Bank 0 Table: User Space (continued)
Name | Addr (0,Hex) | Access | Name | Addr (0,Hex) | Access | Name | Addr (0,Hex) | Access | Name | Addr (0,Hex) | Access |
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DCB03DR2 | 2E | RW |
| 6E |
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| AE |
| ACC_DR3 | EE | RW |
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DCB03CR0 | 2F | # |
| 6F |
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| AF |
| ACC_DR2 | EF | RW |
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| 30 |
| ACB00CR3 | 70 | RW | RDI0RI | B0 | RW |
| F0 |
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| 31 |
| ACB00CR0 | 71 | RW | RDI0SYN | B1 | RW |
| F1 |
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| 32 |
| ACB00CR1 | 72 | RW | RDI0IS | B2 | RW |
| F2 |
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| 33 |
| ACB00CR2 | 73 | RW | RDI0LT0 | B3 | RW |
| F3 |
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| 34 |
| ACB01CR3 | 74 | RW | RDI0LT1 | B4 | RW |
| F4 |
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| 35 |
| ACB01CR0 | 75 | RW | RDI0RO0 | B5 | RW |
| F5 |
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| 36 |
| ACB01CR1 | 76 | RW | RDI0RO1 | B6 | RW |
| F6 |
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| 37 |
| ACB01CR2 | 77 | RW |
| B7 |
| CPU_F | F7 | RL |
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| 38 |
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| 78 |
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| B8 |
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| F8 |
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| 39 |
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| 79 |
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| B9 |
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| F9 |
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| 3A |
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| 7A |
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| BA |
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| FA |
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| 3B |
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| 7B |
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| BB |
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| FB |
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| 3C |
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| 7C |
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| BC |
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| FC |
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| 3D |
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| 7D |
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| BD |
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| FD |
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| 3E |
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| 7E |
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| BE |
| CPU_SCR1 | FE | # |
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| 3F |
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| 7F |
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| BF |
| CPU_SCR0 | FF | # |
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Blank fields are Reserved and must not be accessed. |
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| # Access is bit specific. |
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Table 7. Register Map Bank 1 Table: Configuration Space
Name | Addr (1,Hex) | Access | Name | Addr (1,Hex) | Access | Name | Addr (1,Hex) | Access | Name | Addr (1,Hex) | Access |
PRT0DM0 | 00 | RW |
| 40 |
| ASC10CR0 | 80 | RW |
| C0 |
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PRT0DM1 | 01 | RW |
| 41 |
| ASC10CR1 | 81 | RW |
| C1 |
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PRT0IC0 | 02 | RW |
| 42 |
| ASC10CR2 | 82 | RW |
| C2 |
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PRT0IC1 | 03 | RW |
| 43 |
| ASC10CR3 | 83 | RW |
| C3 |
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PRT1DM0 | 04 | RW |
| 44 |
| ASD11CR0 | 84 | RW |
| C4 |
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PRT1DM1 | 05 | RW |
| 45 |
| ASD11CR1 | 85 | RW |
| C5 |
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PRT1IC0 | 06 | RW |
| 46 |
| ASD11CR2 | 86 | RW |
| C6 |
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PRT1IC1 | 07 | RW |
| 47 |
| ASD11CR3 | 87 | RW |
| C7 |
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PRT2DM0 | 08 | RW |
| 48 |
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| 88 |
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| C8 |
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PRT2DM1 | 09 | RW |
| 49 |
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| 89 |
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| C9 |
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PRT2IC0 | 0A | RW |
| 4A |
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| 8A |
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| CA |
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PRT2IC1 | 0B | RW |
| 4B |
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| 8B |
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| CB |
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| 0C |
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| 4C |
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| 8C |
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| CC |
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| 0D |
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| 4D |
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| 8D |
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| CD |
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| 0E |
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| 4E |
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| 8E |
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| CE |
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| 0F |
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| 4F |
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| 8F |
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| CF |
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| 10 |
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| 50 |
| ASD20CR0 | 90 | RW | GDI_O_IN | D0 | RW |
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| 11 |
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| 51 |
| ASD20CR1 | 91 | RW | GDI_E_IN | D1 | RW |
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| 12 |
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| 52 |
| ASD20CR2 | 92 | RW | GDI_O_OU | D2 | RW |
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| 13 |
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| 53 |
| ASD20CR3 | 93 | RW | GDI_E_OU | D3 | RW |
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| 14 |
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| 54 |
| ASC21CR0 | 94 | RW |
| D4 |
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| 15 |
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| 55 |
| ASC21CR1 | 95 | RW |
| D5 |
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| 16 |
|
| 56 |
| ASC21CR2 | 96 | RW |
| D6 |
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Blank fields are Reserved and must not be accessed. |
|
| # Access is bit specific. |
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Document Number: | Page 12 of 31 |
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