Cypress CY8C24423A, CY8C24223A manual Enable, Gain, 32K Select

CY8C24223A, CY8C24423A

Figure 8. PLL Lock Timing Diagram

PLL

Enable

TPLLSLEW

FPLL

PLL

Gain 0

24 MHz

Figure 9. PLL Lock for Low Gain Setting Timing Diagram

PLL

Enable

TPLLSLEWLOW 24 MHz

FPLL

PLL

Gain 1

Figure 10. External Crystal Oscillator Startup Timing Diagram

32K

Select

F32K2

32 kHz

TOS

Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F24M

Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram

Jitter32k

F32K2

Document Number: 3-12029 Rev. *E Page 22 of 31

[+] Feedback