Cypress CY8C24423A AC Analog Output Buffer Specifications, Bwob, AC External Clock Specifications

CY8C24223A, CY8C24423A

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 25. AC Analog Output Buffer Specifications

Symbol	Description	Min	Typ	Max	Units
TROB	Rising Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	3	μs
	Power = Low
	Power = High	–	–	3	μs
TSOB	Falling Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	3	μs
	Power = Low
	Power = High	–	–	3	μs
SRROB	Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load	0.6	–	–	V/μs
	Power = Low
	Power = High	0.6	–	–	V/μs
SRFOB	Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load	0.6	–	–	V/μs
	Power = Low
	Power = High	0.6	–	–	V/μs
BWOB	Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load	0.8	–	–	MHz
	Power = Low
	Power = High	0.8	–	–	MHz
BWOB	Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load	300	–	–	kHz
	Power = Low
	Power = High	300	–	–	kHz

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 26. AC External Clock Specifications

Symbol	Description	Min	Typ	Max	Units
FOSCEXT	Frequency	0	–	24.24	MHz
–	High Period	20.6	–	–	ns
–	Low Period	20.6	–	–	ns
–	Power Up IMO to Switch	150	–	–	μs

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 27. AC Programming Specifications

Symbol	Description	Min	Typ	Max	Units
TRSCLK	Rise Time of SCLK	1	–	20	ns
TFSCLK	Fall Time of SCLK	1	–	20	ns
TSSCLK	Data Set up Time to Falling Edge of SCLK	40	–	–	ns
THSCLK	Data Hold Time from Falling Edge of SCLK	40	–	–	ns
FSCLK	Frequency of SCLK	0	–	8	MHz
TERASEB	Flash Erase Time (Block)	–	15	–	ms
TWRITE	Flash Block Write Time	–	30	–	ms
TDSCLK	Data Out Delay from Falling Edge of SCLK	–	–	45	ns
Document Number: 3-12029 Rev. *E				Page 26 of 31

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