PRELIMINARY
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B Page 9 of 24
AC Switching Characteristics
Parameters
Description
20 ns 25 ns 45 ns
Unit
Cypress
Parameters
Alt
Parameters Min Max Min Max Min Max
SRAM Read Cycle
tACE tACS Chip Enable Access Time 20 25 45 ns
tRC[15] tRC Read Cycle Time 20 25 45 ns
tAA[16] tAA Address Access Time 20 25 45 ns
tDOE tOE Output Enable to Data Valid 10 12 20 ns
tOHA[16] tOH Output Hold After Address Change 3 3 3 ns
tLZCE[17] tLZ Chip Enable to Output Active 3 3 3 ns
tHZCE[17] tHZ Chip Disable to Output Inactive 8 10 15 ns
tLZOE[17] tOLZ Output Enable to Output Active 0 0 0 ns
tHZOE[17] tOHZ Output Disable to Output Inactive 8 10 15 ns
tPU[14] tPA Chip Enable to Power Active 0 0 0 ns
tPD[14] tPS Chip Disable to Power Standby 20 25 45 ns
tDBE - Byte Enable to Data Valid 10 12 20 ns
tLZBE - Byte Enable to Output Active 0 0 0 ns
tHZBE - Byte Disable to Output Inactive 8 10 15 ns
SRAM Write Cycle
tWC tWC Write Cycle Time 20 25 45 ns
tPWE tWP Write Pulse Width 15 20 30 ns
tSCE tCW Chip Enable To End of Write 15 20 30 ns
tSD tDW Data Setup to End of Write 8 10 15 ns
tHD tDH Data Hold After End of Write 0 0 0 ns
tAW tAW Address Setup to End of Write 15 20 30 ns
tSA tAS Address Setup to Start of Write 0 0 0 ns
tHA tWR Address Hold After End of Write 0 0 0 ns
tHZWE[17,18] tWZ Write Enable to Output Disable 8 10 15 ns
tLZWE[17] tOW Output Active after End of Write 3 3 3 ns
tBW - Byte Enable to End of Write 15 20 30 ns
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled[15, 16, 19]
$GGUHVV
'DWD2XWSXW
$GGUHVV9DOLG
3UHYLRXV'DWD9DOLG 2XWSXW'DWD9DOLG
W5&
W$$
W2+$
Notes
15.WE must be HIGH during SRAM read cycles.
16.Device is continuously selected with CE, OE and BHE / BLE LOW.
17.Measured ±200 mV from steady state output voltage.
18.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19.HSB must remain HIGH during READ and WRITE cycles.
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