PRELIMINARY
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B Page 12 of 24
AutoStore/Power Up RECALLParameters Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tHRECALL [21] Power Up RECALL Duration 20 20 20 ms
tSTORE [22] STORE Cycle Duration 8 8 8 ms
tDELAY [23] Time Allowed to Complete SRAM Cycle 20 25 25 ns
VSWITCH Low Voltage Trigger Level 2.65 2.65 2.65 V
tVCCRISE VCC Rise Time 150 15 0 150 μs
VHDIS[14] HSB Output Driver Disable Voltage 1.9 1.9 1.9 V
tLZHSB HSB To Output Active Time 5 5 5 μs
tHHHD HSB High Active Time 500 500 500 ns
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL[24]
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9+',6
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W+++' W+++'
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W'(/$<
W/=+6% W/=+6%
W+5(&$//
W+5(&$//
+6%287
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32:(5
83
5(&$//
5HDG:ULWH
,QKLELWHG
5:,
32:(583
5(&$//
5HDG:ULWH %52:1
287
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32:(583
5(&$//
5HDG:ULWH 32:(5
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1RWH 1RWH
1RWH
Notes
21.tHRECALL starts from the time VCC rises above VSWITCH.
22.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
23.On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY
.
24.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
25.HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
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